IEICE Trans

Yasuhiro MORITA

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing Hiroki NOGUCHI Yusuke IGUCHI Hidehiro FUJIWARA Shunsuke OKUMURA Yasuhiro MORITA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 543-552 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: 8T SRAM cell, 10T SRAM cell, low-power SRAM, non-precharge SRAM, two-port SRAM, video processing,
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Area Comparison between 6T and 8T SRAM Cells in Dual-V_dd Scheme and DVS Scheme Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2695-2702 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: 6T SRAM cell, 8T SRAM cell, V_th variation,
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Area Optimization in 6T and 8T SRAM Cells Considering V_th Variation in Future Processes Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1949-1956 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Next-Generation Memory for SoC Keyword: 6T SRAM cell, 8T SRAM cell, V_th variation,
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A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3634-3641 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: SRAM, DVS, V_th-variation-tolerant, low power,
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Vertical Partitioning Method for Secret Sharing Distributed Database System Toshiyuki MIYAMOTO Yasuhiro MORITA Sadatoshi KUMAGAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/11/01 Vol. E89-A No. 11 pp. 3244-3249 Type of Manuscript: Special Section PAPER (Special Section on Concurrent/Hybrid Systems: Theory and Applications) Category: Concurrent Systems Keyword: distributed database system, multi-agent systems, secret sharing scheme, vertical partitioning,
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Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Jun TAKEMURA Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3290-3297 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: low power, dynamic voltage frequency scaling (DVFS), adaptive body biasing, V_dd-hopping, V_th-hopping,
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A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU Hideo OHIRA Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 457-465 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: MPEG4 encoder, low power, feed-forward voltage control, multi-regulated voltage CPU,
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