Memory Allocation for Multi-Resolution Image Processing
Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2386-2397
Type of Manuscript:  PAPER
Category: VLSI Systems
high-level synthesisinterconnection-aware architecturestereo vision
 Summary | Full Text:PDF

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3516-3522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
stereo visionFPGAschedulingallocation
 Summary | Full Text:PDF