IEICE Trans

Yasuhiko NAKASHIMA

A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness Thi Thu Thao KHONG Takashi NAKADA Yasuhiko NAKASHIMA
Publication: Publication Date: 2022/07/01 Vol. E105-D No. 7 pp. 1308-1319 Type of Manuscript: PAPER Category: Image Recognition, Computer Vision Keyword: Bayesian neural network, convolutional neural network, adversarial robustness, image classification,
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GPGPU Implementation of Variational Bayesian Gaussian Mixture Models Hiroki NISHIMOTO Renyuan ZHANG Yasuhiko NAKASHIMA
Publication: Publication Date: 2022/03/01 Vol. E105-D No. 3 pp. 611-622 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: GPGPU, Gaussian mixture model, variational Bayes, machine learning, clustering,
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Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks Thi Thu Thao KHONG Takashi NAKADA Yasuhiko NAKASHIMA
Publication: Publication Date: 2021/11/01 Vol. E104-D No. 11 pp. 1981-1991 Type of Manuscript: PAPER Category: Image Recognition, Computer Vision Keyword: Deep Neural Network, Bayesian Neural Network, image classification, adversarial attacks, adversarial training,
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SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks Thi Diem TRAN Yasuhiko NAKASHIMA
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 pp. 319-329 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: primary visual cortex, image classification, convolutional neural network, hardware architecture, FPGA, feature extraction,
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A Feasibility Study of Multi-Domain Stochastic Computing Circuit Tati ERLINA Renyuan ZHANG Yasuhiko NAKASHIMA
Publication: Publication Date: 2021/05/01 Vol. E104-C No. 5 pp. 153-163 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: stochastic computing, multi-domain, approximate computing, MAC,
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Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing Ryuta SHINGAI Yuria HIRAGA Hisakazu FUKUOKA Takamasa MITANI Takashi NAKADA Yasuhiko NAKASHIMA
Publication: Publication Date: 2020/10/01 Vol. E103-D No. 10 pp. 2072-2082 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: convolutional neural network, edge computing, distributed neural network, video compression,
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Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth Jun IWAMOTO Yuma KIKUTANI Renyuan ZHANG Yasuhiko NAKASHIMA
Publication: Publication Date: 2020/03/01 Vol. E103-D No. 3 pp. 578-589 Type of Manuscript: PAPER Category: Computer System Keyword: systolic array, reconfigurable memory space, memory bandwidth,
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A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks Yan CHEN Jing ZHANG Yuebing XU Yingjie ZHANG Renyuan ZHANG Yasuhiko NAKASHIMA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 580-584 Type of Manuscript: BRIEF PAPER Category: Keyword: data locality, ReRAM, convolutional neural networks, row-column-oriented access,
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Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation Renyuan ZHANG Takashi NAKADA Yasuhiko NAKASHIMA
Publication: Publication Date: 2019/07/01 Vol. E102-A No. 7 pp. 878-885 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: approximate computing, analog calculation unit, support vector regression, vector-computation,
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Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems Dinh-Dung LE Duc-Phuc NGUYEN Thi-Hong TRAN Yasuhiko NAKASHIMA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2210-2212 Type of Manuscript: Special Section LETTER (Special Section on Information Theory and Its Applications) Category: Communication Theory and Signals Keyword: visible light communication, VLC, soft-decision decoding, Polar code,
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A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing Hoang-Gia VU Shinya TAKAMAEDA-YAMAZAKI Takashi NAKADA Yasuhiko NAKASHIMA
Publication: Publication Date: 2018/02/01 Vol. E101-D No. 2 pp. 288-302 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Device and Architecture Keyword: checkpointing, FPGA, dependability, tree-based,
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Performance Optimization of Light-Field Applications on GPU Yuttakon YUTTAKONKIT Shinya TAKAMAEDA-YAMAZAKI Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/12/01 Vol. E99-D No. 12 pp. 3072-3081 Type of Manuscript: PAPER Category: Computer System Keyword: light-field image processing, GPU optimization, GPU architecture,
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Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators Yoshikazu INAGAKI Shinya TAKAMAEDA-YAMAZAKI Jun YAO Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/12/01 Vol. E98-D No. 12 pp. 2141-2149 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: CGRA, coarse grained reconfigurable architecture, accelerator, library, stencil, optimization,
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FOREWORD Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/12/01 Vol. E98-D No. 12 pp. 2047-2047 Type of Manuscript: FOREWORD Category: Keyword:
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Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults Yukihiro SASAGAWA Jun YAO Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/12/01 Vol. E97-D No. 12 pp. 3083-3091 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: adaptive redundancy, setup error recovery, DVS, low power, AVF, ILP,
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A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction Jun YAO Yasuhiko NAKASHIMA Naveen DEVISETTI Kazuhiro YOSHIMURA Takashi NAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/12/01 Vol. E97-D No. 12 pp. 3092-3100 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: reconfigurable architectures, multi-core processing, energy efficiency,
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Selective Check of Data-Path for Effective Fault Tolerance Tanvir AHMED Jun YAO Yuko HARA-AZUMI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1592-1601 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: low power, fault-tolerant computing, FU array,
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Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/01/01 Vol. E96-D No. 1 pp. 1-8 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: multiparty communication complexity, quantum computation, quantum nondeterminism, tensor rank,
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RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2319-2329 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: adaptive redundancy, setup error recovery, DVS, low power, AVF,
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Quantum Walks on the Line with Phase Parameters Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/03/01 Vol. E95-D No. 3 pp. 722-730 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –) Category: Keyword: quantum computation, random walks, quantum walks, asymptotic approximation,
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An Instruction Mapping Scheme for FU Array Accelerator Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/02/01 Vol. E94-D No. 2 pp. 286-297 Type of Manuscript: PAPER Category: Computer System Keyword: instruction mapping, FU array, coarse-grained reconfigurable architecture,
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ReVolver/C40: A Scalable Parallel Computer for Volume Rendering--Design and Implementation-- Shin-ichiro MORI Tomoaki TSUMURA Masahiro GOSHIMA Yasuhiko NAKASHIMA Hiroshi NAKASHIMA Shinji TOMITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 2006-2015 Type of Manuscript: Special Section PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: volume rendering, parallel processing, scalable architecture, visualization,
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