Yasue YAMAMOTO


A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI
Yasue YAMAMOTO Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Shinichi SUMI Yasuhiro AGATA Hirohito KIKUKAWA Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 1129-1137
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
non-volatile memorysingle poly gatedifferential cellCMOS logic processSystem-on-Chip (SoC)
 Summary | Full Text:PDF

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering
Yasue YAMAMOTO Takeshi HIDAKA Hiroki NAKAMURA Hiroshi SAKURABA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/04/01
Vol. E89-C  No. 4  pp. 560-567
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
Surrounding Gate Transistor (SGT)scalingintrinsic channelgate work function engineering
 Summary | Full Text:PDF