Xiongxin ZHAO

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
Xiongxin ZHAO Zhixiang CHEN Xiao PENG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2623-2632
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAX, bit-serial, fully-parallel, layered scheduling, performance aware, advanced dynamic quantization, quasi-cyclic, low-density parity-check codes, 
 Summary | Full Text:PDF
A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2384-2391
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAX, bit-serial, layered scheduling, QC-LDPC, 
 Summary | Full Text:PDF
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Zhixiang CHEN Xiao PENG Xiongxin ZHAO Leona OKAMURA Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2587-2596
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WPAN, IEEE802.15.3c, LDPC decoder, high data rate, power-efficient, 
 Summary | Full Text:PDF
Generic Permutation Network for QC-LDPC Decoder
Xiao PENG Xiongxin ZHAO Zhixiang CHEN Fumiaki MAEHARA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2551-2559
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
LDPC decoder, reconfigurable, permutation network, parallelism, 
 Summary | Full Text:PDF
Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
Xiao PENG Zhixiang CHEN Xiongxin ZHAO Fumiaki MAEHARA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 270-278
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
permutation, banyan network, LDPC decoder, reconfigurable, 
 Summary | Full Text:PDF