Xincun JI


A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks
Meng XU Xincun JI Jianhui WU Meng ZHANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/04/01
Vol. E96-B  No. 4  pp. 939-947
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
LDPCMultimedia Wireless Sensor Networkslow power designlayered decodingmemory bypassing schemeBenes network
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Energy-Aware Task Scheduling for Real-Time Systems with Discrete Frequencies
Dejun QIAN Zhe ZHANG Chen HU Xincun JI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4  pp. 822-832
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
real-time systemlow power designdynamic voltage scalingstochastic speed scheduling
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An 11.2-mW 5-GHz CMOS Frequency Synthesizer with Low Power Prescaler for Zigbee Application
Xincun JI Fuqing HUANG Jianhui WU Longxing SHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 375-378
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
CMOSWSNhalf-integer phase-switching prescalerfrequency synthesizer
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A Modified BP Algorithm for LDPC Decoding Based on Minimum Mean Square Error Criterion
Meng XU Xincun JI Jianhui WU Meng ZHANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/05/01
Vol. E93-B  No. 5  pp. 1256-1259
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
LDPCMMSEBP algorithmlinear approximation
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Duty Cycle Corrector for Pipelined ADC with Low Added Jitter
Zhengchang DU Jianhui WU Shanli LONG Meng ZHANG Xincun JI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 864-866
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
duty cyclepipelined ADCcontinuous-time integratorlow added jitter
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