IEICE Trans

Xiaoqing WEN

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang LI Xiaoqing WEN Kohei MIYASE Stefan HOLST Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2310-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: at-speed scan testing, IR-drop, capture-power-safety, logic path, clock path, clock stretch, test quality,
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Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures Tian CHEN Dandan SHEN Xin YI Huaguo LIANG Xiaoqing WEN Wei WANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/11/01 Vol. E99-D No. 11 pp. 2672-2681 Type of Manuscript: PAPER Category: Computer System Keyword: low power test, data compression, LFSR, X-filling,
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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/10/01 Vol. E97-D No. 10 pp. 2706-2718 Type of Manuscript: PAPER Category: Dependable Computing Keyword: at-speed scan-based logic BIST, capture power safety, masking, IR-drop, transition delay fault, long sensitized path,
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A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Kohei MIYASE Ryota SAKAI Xiaoqing WEN Masao ASO Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 2003-2011 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: at-speed testing, ATPG, IR-drop, test power reduction, low power test,
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Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/06/01 Vol. E94-D No. 6 pp. 1216-1226 Type of Manuscript: PAPER Category: Dependable Computing Keyword: ATPG, X-bit, X-identification, X-filling,
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A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Yuta YAMATO Xiaoqing WEN Kohei MIYASE Hiroshi FURUKAWA Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/04/01 Vol. E94-D No. 4 pp. 833-840 Type of Manuscript: PAPER Category: Dependable Computing Keyword: X-filling, genetic algorithm, launch switching activity, IR-drop, at-speed scan testing,
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1309-1318 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking,
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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Kohei MIYASE Xiaoqing WEN Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA Patrick GIRARD Laung-Terng WANG Mohammad TEHRANIPOOR
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 pp. 2-9 Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs) Category: Keyword: power supply noise, test relaxation, X-filling, clock-gating, test compaction,
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On Detection of Bridge Defects with Stuck-at Tests Kohei MIYASE Kenta TERASHIMA Xiaoqing WEN Seiji KAJIHARA Sudhakar M. REDDY
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 683-689 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: defect based testing, test vector generation, test vector modification, bridging faults, fault extraction,
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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Yuta YAMATO Yusuke NAKAMURA Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 667-674 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, X-fault model, per-test, via,
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A Novel ATPG Method for Capture Power Reduction during Scan Testing Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/09/01 Vol. E90-D No. 9 pp. 1398-1405 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Yu HU Yinhe HAN Xiaowei LI Huawei LI Xiaoqing WEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/10/01 Vol. E89-D No. 10 pp. 2616-2625 Type of Manuscript: PAPER Category: Dependable Computing Keyword: compression, run-length coding, random access scan, power dissipation, test application time,
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A New Method for Low-Capture-Power Test Generation for Scan Testing Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1679-1686 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores Yinhe HAN Yu HU Xiaowei LI Huawei LI Anshuman CHANDRA Xiaoqing WEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/09/01 Vol. E88-D No. 9 pp. 2126-2134 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SOC testing, wrapper design, scan slices, overlapping,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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Transistor Leakage Fault Diagnosis for CMOS Circuits Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 697-705 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,
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Improving Random Pattern Testability with Partial Circuit Duplication Approach Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 654-659 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Design for Testability Keyword: partial circuit duplication, random testing, design for testability, built-in self-test,
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Testing of k-FR Circuits under Highly Observable Condition Xiaoqing WEN Hideo TAMAMOTO Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 830-838 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: testable design, fault testing, highly observable condition, circuit conversion,
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