IEICE Trans

Xianlong HONG

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs Kan WANG Sheqin DONG Yuchun MA Yu WANG Xianlong HONG Jason CONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2490-2498 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: leakage power, TSV, delay-power-temperature dependence,
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Efficient Power Network Analysis with Modeling of Inductive Effects Shan ZENG Wenjian YU Xianlong HONG Chung-Kuan CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/06/01 Vol. E93-A No. 6 pp. 1196-1203 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: frequency-domain analysis, inductive modeling, partial reluctance, power network, time-domain voltage response,
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Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation Yuchun MA Xin LI Yu WANG Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2979-2989 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: 3D ICs, incremental floorplanning, thermal, MILP,
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Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures Shan ZENG Wenjian YU Jin SHI Xianlong HONG Chung-Kuan CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1476-1484 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-frequency effect, inductance modeling, parasitic extraction, partial reluctance, power/ground grid,
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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model Yanming JIA Yici CAI Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3783-3792 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: VLSI, buffer insertion, physical design, DFM, dummy fill,
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Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan Xiaoyi WANG Jin SHI Yici CAI Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3443-3450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power/ground network, floorplan, IR drop,
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Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage Liangpeng GUO Yici CAI Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 pp. 2084-2090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: voltage island, level converter, low power, placement,
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Low Power Gated Clock Tree Driven Placement Weixiang SHEN Yici CAI Xianlong HONG Jiang HU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 595-603 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: gated clock tree, activity-aware, register placement,
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Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration Yibo WANG Yici CAI Xianlong HONG Yi ZOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 1028-1037 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: interconnect optimization, accurate delay model, low power, buffer insertion,
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Voltage Island Generation in Cell Based Dual-Vdd Design Yici CAI Bin LIU Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 267-273 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-Vdd, layout, placement, voltage island, voltage assignment,
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Navigating Register Placement for Low Power Clock Network Design Yongqiang LU Chin-Ngai SZE Xianlong HONG Qiang ZHOU Yici CAI Liang HUANG Jiang HU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3405-3411 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan and Placement Keyword: clock network, standard cell, quadratic placement, prescribed skew,
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Timing-Driven Global Routing with Efficient Buffer Insertion Jingyu XU Xianlong HONG Tong JING
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 3188-3195 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: VLSI layout, global routing, timing-driven, buffer insertion, routability,
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A Fast Delay Computation for the Hybrid Structured Clock Network Yi ZOU Yici CAI Qiang ZHOU Xianlong HONG Sheldon X.-D. TAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/07/01 Vol. E88-A No. 7 pp. 1964-1970 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock networks, simulation, analysis, delay, Elmore delay,
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Crosstalk and Congestion Driven Layer Assignment Algorithm Bin LIU Yici CAI Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/06/01 Vol. E88-A No. 6 pp. 1565-1572 Type of Manuscript: PAPER Category: Circuit Theory Keyword: congestion, crosstalk, layer assignment, VLSI,
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Partial Random Walks for Transient Analysis of Large Power Distribution Networks Weikun GUO Sheldon X.-D. TAN Zuying LUO Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3265-3272 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: random walks, on-chip power distribution, simulation, power/ground networks,
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A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery Jingjing FU Zuying LUO Xianlong HONG Yici CAI Sheldon X.-D. TAN Zhu PAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3273-3280 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: power delivery, optimization, decoupling capacitor, non-linear programming,
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A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Jingyu XU Xianlong HONG Tong JING Yici CAI Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3158-3167 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: high performance design, global routing, timing-driven, coupling effects,
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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing Sheqin DONG Xianlong HONG Song CHEN Xin QI Ruijie WANG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3136-3147 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: floorplan, placement, solution space smoothing,
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VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2697-2704 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Keyword: floorplan, corner block list, simulated annealing, boundary constraints,
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