Wu-Shiung FENG


On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions
Ming-Hong LAI Chia-Chi CHU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2  pp. 411-414
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
VLSI interconnectKrylov subspace order reductionsstructure-preserving reductionsadjoint networks
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Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm
Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2  pp. 415-418
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
model-order reductionMIMOglobal Arnoldi algorithmLyapunov equationadditive perturbed system
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The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions
Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10  pp. 2706-2716
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Modelling, Systems and Simulation
Keyword: 
model-order reductionmultiple-inputs multiple-outputsglobal Lanczos algorithmmatrix Krylov subspacemultiple point moment matching
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MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm
Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6  pp. 792-802
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
rational Arnoldi algorithmglobal Arnoldi algorithmsmodel reductionsinterconnectKrylov subspaceMIMO
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An Adjoint Network Approach for RLCG Interconnect Model Order Reductions
Chia-Chi CHU Herng-Jer LEE Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 439-447
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
RLCG interconnectsmodel-order reductionArnoldi algorithmLanczos algorithmadjoint network
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Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions
Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3573-3576
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
two-sided projection-based methodinterconnect model reductionnonsymmetric Pade via Lanczos algorithmperturbation matrix
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Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise
Herng-Jer LEE Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1186-1195
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: CAD
Keyword: 
uniform and non-uniform distributed coupled RLC interconnectsinductive crosstalk noisemoment computationsKryolv subspace model-order reductions
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A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers
Ming-Chang SUN Ying-Haw SHU Shing TENQCHEN Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/03/01
Vol. E88-C  No. 3  pp. 420-428
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CMOSradio frequencycascodelow noise amplifierinput matching
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Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions
Chia-Chi CHU Herng-Jer LEE Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2  pp. 533-537
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
interconnectmodel reductionsArnordi iterationsresidual error
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Applications of Tree/Link Partitioning for Moment Computations of General Lumped R(L)C Interconnect Networks with Multiple Resistor Loops
Herng-Jer LEE Ming-Hong LAI Chia-Chi CHU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3281-3292
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
moment computationsresistor looptree/link partitionreduced ordered binary decision diagram
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Indirect Approach for Designing Low-Order Linear-Phase IIR Filters Using the Rational Arnoldi Method with Adaptive Orders
Herng-Jer LEE Chia-Chi CHU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8  pp. 2018-2028
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Filter Design
Keyword: 
FIRIIRlow-orderlinear-phase filtermulti-point Pade approximationsKrylov subspacerational Arnoldi method
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Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise
Herng-Jer LEE Chia-Chi CHU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2952-2964
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
crosstalk noise estimationcoupled RLC-tree modelhigh-speed VLSI interconnectsrecursive moment computations
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Novel Gm-C Realizations of nth-Order Filters
Cheng-Chung HSU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/01/01
Vol. E84-A  No. 1  pp. 339-346
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
Gm-C filtersmultiple loop feedbackactive-RC filterOTA
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Structural Generation of Current-Mode Filters Using Tunable Multiple-Output OTAs and Grounded Capacitors
Cheng-Chung HSU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/09/25
Vol. E83-A  No. 9  pp. 1778-1785
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
current-mode filteroperational transconductance amplifier (OTA)multiple-loop feedbackactive-RC filtercontinuous-time filter
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OTA-C Based BIST Structure for Analog Circuits
Cheng-Chung HSU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/04/25
Vol. E83-A  No. 4  pp. 771-773
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
built-in self-test (BIST)operational transconductance amplifier (OTA)analog circuitfault diagnosistesting
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An Algorithm for Estimating Bottleneck Effect in Series-Parallel Tree Circuits
Molin CHANG Wang-Jin CHEN Jyh-Herng WANG Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/11/25
Vol. E81-A  No. 11  pp. 2400-2406
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
waveform-based switch-level timing simulatorslope estimationbottleneck effect
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A Recursive Algorithm for Estimating the Internal Charge Sharing Effect in RC Tree Circuits
Molin CHANG Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 913-923
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
charge sharing effectswitch-level timing simulatormodified threaded binary treeRC tree
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Pattern-Based Maximal Power Estimation for VLSI Chip Design
Wang-Jin CHEN Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/11/25
Vol. E80-A  No. 11  pp. 2300-2307
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
maximal power dissipationsimulated annealingwalk throughpower estimationpower optimization
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