Woo Young CHOI

Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory
Woo Young CHOI Min Su HAN Boram HAN Dongsun SEO Il Hwan CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5  pp. 714-717
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
nano electro mechanical nonvolatile memory, pull-in voltage, 
 Summary | Full Text:PDF
L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
Sang Wan KIM Woo Young CHOI Min-Chul SUN Hyun Woo KIM Jong-Ho LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5  pp. 634-638
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
L-shaped TFETs, subthreshold swing, steep slope, complementary logic function, 
 Summary | Full Text:PDF
Analytical Model of Nano-Electromechanical (NEM) Nonvolatile Memory Cells
Boram HAN Woo Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5  pp. 914-916
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
nano-electromechanical (NEM) non-volatile memory cell, fringe field effect, beam width, 
 Summary | Full Text:PDF
Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)
Gibong LEE Woo Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5  pp. 910-913
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
low power, propagation delay, energy dissipation, tunneling field-effect transistor (TFET), 
 Summary | Full Text:PDF
Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time
Woojun LEE Kwangsoo KIM Woo Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 110-115
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
1T DRAM, capacitorless DRAM, low voltage, data retention time, 
 Summary | Full Text:PDF
Design and Simulation of Asymmetric MOSFETs
Jong Pil KIM Woo Young CHOI Jae Young SONG Seongjae CHO Sang Wan KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 978-982
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
Keyword: 
asymmetric MOSFET, LDD, mesa structure, sidewall spacer gate, 
 Summary | Full Text:PDF