Won-Young JUNG

A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique
Ji-Hoon LIM Won-Young JUNG Yong-Ju KIM Inchae SONG Jae-Kyung WEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/02/01
Vol. E96-C  No. 2  pp. 277-284
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
switching mode power supply (SMPS), digital pulse width modulation (DPWM), over/under-shoot, high efficiency, 
 Summary | Full Text:PDF
A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process
Jae-Young PARK Dae-Woo KIM Young-Sang SON Jong-Kyu SONG Chang-Soo JANG Won-Young JUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5  pp. 796-801
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
electrostatic discharge (ESD), non-snapback characteristics, gate-coupled effect, isolated parasitic capacitance, Bipolar-CMOS-DMOS process, 
 Summary | Full Text:PDF
A Precision Floating-Gate Mismatch Measurement Technique for Analog Application
Won-Young JUNG Jong-Min KIM Jin-Soo KIM Taek-Soo KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5  pp. 780-785
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
mismatch measurement, floating-gate capacitance measurement method, MIM capacitance, 
 Summary | Full Text:PDF
On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
Jae-Young PARK Jong-Kyu SONG Dae-Woo KIM Chang-Soo JANG Won-Young JUNG Taek-Soo KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 625-630
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Analog/RF Devices
Keyword: 
electrostatic discharge (ESD), charged device model (CDM), very-fast transmission line pulse system, low voltage triggered SCR devices, radio pulse integrated circuits (RF ICs), 
 Summary | Full Text:PDF
A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
Jae-Young PARK Jong-Kyu SONG Chang-Soo JANG San-Hong KIM Won-Young JUNG Taek-Soo KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 671-675
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
ESD (electrostatic discharge) ESD power clamp circuit, latch-up, stacked-bipolar devices, 
 Summary | Full Text:PDF
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches
Won-Young JUNG Hyungon KIM Yong-Ju KIM Jae-Kyung WEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1177-1184
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
process-induced variation, interconnect worstcase optimization, effective common geometry (ECG), accumulated maximum probability (AMP), non-normal distribution, 
 Summary | Full Text:PDF
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips
Ji-Hoon LIM Jong-Chan HA Won-Young JUNG Yong-Ju KIM Jae-Kyung WEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/03/01
Vol. E90-C  No. 3  pp. 644-648
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
dynamic voltage frequency scaling (DVFS), voltage level shifter, low-power design, 
 Summary | Full Text:PDF
Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards
Yong-Ju KIM Won-Young JUNG Jae-Kyung WEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/07/01
Vol. E89-C  No. 7  pp. 1097-1105
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
partial equivalent electrical circuit (PEEC), power distribution network (PDN), path-based equivalent circuit (PBEC), 
 Summary | Full Text:PDF
Interconnect Modeling in Deep-Submicron Design
Won-Young JUNG Soo-Young OH Jeong-Taek KONG Keun-Ho LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8  pp. 1311-1316
Type of Manuscript:  INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Circuit Applications
Keyword: 
statistical interconnect library generation, interconnect modeling, Monte Carlo method, process variation, 
 Summary | Full Text:PDF