Wataru TAKAHASHI

Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture
Takashi KISHIMOTO Wataru TAKAHASHI Kazutoshi WAKABAYASHI Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2328-2334
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
simulated annealing based placement algorithm, coarse-grained and fine-grained reconfigurable architectures, 
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A Robust Speech Communication into Smart Info-Media System
Yoshikazu MIYANAGA Wataru TAKAHASHI Shingo YOSHIZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/11/01
Vol. E96-A  No. 11  pp. 2074-2080
Type of Manuscript:  INVITED PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: 
Keyword: 
smart info-media system, robust speech recognition, voice activity detection, speech rejection, ASIC, low power consumption design, 
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Fixed Point Data Type Modeling for High Level Synthesis
Benjamin CARRION SCHAFER Yusuke IGUCHI Wataru TAKAHASHI Shingo NAGATANI Kazutoshi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 361-368
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
fixed point, data types, high level synthesis, automation, modeling, 
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Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis
Hidefumi KUROKAWA Hiroyuki IKEGAMI Motohide OTSUBO Kiyoshi ASAO Kazuhisa KIRIGAYA Katsuya MISU Satoshi TAKAHASHI Tetsuji KAWATSU Kouji NITTA Hiroshi RYU Kazutoshi WAKABAYASHI Minoru TOMOBE Wataru TAKAHASHI Akira MUKOUYAMA Takashi TAKENAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 787-798
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
C-based design, behavioral synthesis, verification, design productivity, model abstraction, 
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Schedule-Clock-Tree Routing for Semi-Synchronous Circuits
Kazunori INOUE Wataru TAKAHASHI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2431-2439
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
clock-tree, clock-scheduling, semi-synchronous circuit, deferred-merge embedding, 
 Summary | Full Text:PDF