Wangning LONG

Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2725-2736
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
alternative wire, logic transformation, logic synthesis, 
 Summary | Full Text:PDF(433.7KB)
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
Yu-Liang WU Wangning LONG Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6  pp. 1131-1137
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
rewiring, logic synthesis, circuit minimization, redundancy, 
 Summary | Full Text:PDF(895.7KB)