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| Vasily G. MOSHNYAGA
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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A
No. 4
pp. 862-868
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, cache, leakage, | | | Summary | Full Text:PDF | |
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A
No. 4
pp. 799-805
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, instruction ROM, embedded systems, encoding, | | | Summary | Full Text:PDF | |
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2
pp. 279-287
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
cache, low power, look up, run time, | | | Summary | Full Text:PDF | |
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Issue Queue Energy Reduction through Dynamic Voltage Scaling
Vasily G. MOSHNYAGA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2
pp. 272-278
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
issue queue, computer architecture, low power, voltage scaling, | | | Summary | Full Text:PDF | |
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Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA Hiroshi TSUJI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11
pp. 2762-2768
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword:
cache, processor architecture, low-power, | | | Summary | Full Text:PDF | |
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A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs
Vasily G. MOSHNYAGA Keikichi TAMARU | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D
No. 10
pp. 1389-1395
Type of Manuscript:
Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword:
high-level synthesis, ASIC design methodology, | | | Summary | Full Text:PDF | |
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