Tsuyoshi IWAGAKI


Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2563-2570
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
asynchronous on-chip interconnectCHAINstuck-at faulttest schedulinginteger linear programming
 Summary | Full Text:PDF(1.3MB)

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4  pp. 1067-1081
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapath synthesisdelay variationregister assignmenthold timing constraintbackward-data-direction clockinginteger linear programming
 Summary | Full Text:PDF(589.9KB)

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1096-1105
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesisdelay variationregister assignmentsetup and hold constraintsminimum delay compensationinteger linear programming
 Summary | Full Text:PDF(347.8KB)

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1044-1053
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesisdelay variationregister assignmentsetup and hold constraints
 Summary | Full Text:PDF(331.5KB)

A Low Power Deterministic Test Using Scan Chain Disable Technique
Zhiqiang YOU Tsuyoshi IWAGAKI Michiko INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/06/01
Vol. E89-D  No. 6  pp. 1931-1939
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
low power testingfull scan testingdeterministic testscan chain disabletabu search algorithm
 Summary | Full Text:PDF(638.3KB)

A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3200-3207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
controllerdelay faultnon-scan designinvalid test state and transition generatorat-speed test
 Summary | Full Text:PDF(463.8KB)