Tsutomu YOSHIMURA

A 10 Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 µm SOI/CMOS Technology
Tsutomu YOSHIMURA Kimio UEDA Jun TAKASOH Harufusa KONDOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 643-651
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
10 Gb/s Ethernet, clock and data recovery, lock detector, SOI/CMOS process, 
 Summary | Full Text:PDF
Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits
Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1697-1704
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
silicon on insulator (SOI), complementary metal oxide semiconductor (CMOS), emitter coupled logic (ECL), 
 Summary | Full Text:PDF
A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
Harufusa KONDOH Hiromi NOTANI Tsutomu YOSHIMURA Hiroshi SHIBATA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 381-388
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
PLL, PFD, VCO, CMOS, ATM, 
 Summary | Full Text:PDF