IEICE Trans

Tsutomu YOSHIHARA

Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters Xutao LI Minjie CHEN Hirofumi SHINOHARA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2016/02/01 Vol. E99-B No. 2 pp. 356-363 Type of Manuscript: PAPER Category: Energy in Electronics Communications Keyword: boost converters, sensorless control, robust H∞ control, closed-loop characteristics,
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Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator Hao ZHANG Mengshu HUANG Yimeng ZHANG Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 859-866 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: voltage reference, subthreshold, self-cascode, body effect, ultra-low power, low output,
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An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme Mengshu HUANG Yimeng ZHANG Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 439-446 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: charge sharing, dual charge pump, power efficiency,
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An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory Mengshu HUANG Leona OKAMURA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 968-976 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: hybrid decoupling, charge pump, program noise suppression,
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An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic Yimeng ZHANG Leona OKAMURA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 605-612 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: adiabatic logic, boost logic, low energy dissipation, pipeline multiplier,
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A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 pp. 2020-2027 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded memory, DRAM, voltage margin, low voltage, system on chip,
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Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 622-629 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Memory Keyword: CMOS, Ternary CAM, network, refresh,
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Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories Kiyohiro FURUTANI Takeshi HAMAMOTO Takeo MIKI Masaya NAKANO Takashi KONO Shigeru KIKUDA Yasuhiro KONISHI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/02/01 Vol. E88-C No. 2 pp. 255-263 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: DRAM, redundancy, high speed, high density,
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Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 253-259 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, floating body, body control, high speed, low power,
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Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory Shin-ichi KOBAYASHI Hiroaki NAKAI Yuichi KUNORI Takeshi NAKAYAMA Yoshikazu MIYAWAKI Yasushi TERADA Hiroshi ONODA Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/25 Vol. E77-C No. 5 pp. 784-790 Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories Yoshikazu MIYAWAKI Takeshi NAKAYAMA Shin-ichi KOBAYASHI Natsuo AJIKA Makoto OHI Yasushi TERADA Hideaki ARIMA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/25 Vol. E75-C No. 4 pp. 481-486 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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An Experimental 16 kbit Nonvolatile Random Access Memory Kazuo KOBAYASHI Yasushi TERADA Masanori HAYASHIKOSHI Takeshi NAKAYAMA Hideaki ARIMA Takayuki MATSUKAWA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/02/25 Vol. E73-E No. 2 pp. 260-264 Type of Manuscript: PAPER Category: Integrated Electronics Keyword:
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Mechanism of Bit Line Mode Soft Error for DRAM Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/11/25 Vol. E70-E No. 11 pp. 1060-1061 Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE) Category: Semiconductor Devices Keyword:
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