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Tsutomu SASAO

A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs Tsutomu SASAO
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1574-1582 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: random function, CAM, content-addressable memory, linear decomposition, linear transformation, statistical analysis, update method,
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A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1583-1591 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: index generation functions, linear decomposition, incompletely specified functions, balanced decision tree, content-addressable memory, logic design, heuristic,
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A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-D No. 2 pp. 262-271 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: CAM, IP lookup, index generation unit, FPGA,
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A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix Tsutomu SASAO Yuta URANO Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2427-2433 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: minimal cover, linear transformation, functional decomposition, incompletely specified function, logic minimization,
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Head-Tail Expressions for Interval Functions Infall SYAFALNI Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/10/01 Vol. E97-A No. 10 pp. 2043-2054 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: prefix sum-of-products, head-tail expressions, TCAM,
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A Packet Classifier Based on Prefetching EVMDD (k) Machines Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2243-2252 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: many core, packet classification, decision diagram, multi-valued logic,
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On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER Mitchell A. THORNTON Theodore W. MANIKAS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2234-2242 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: minimization algorithm of the number of edges, EVMDDs, grouping variables for optimization of decision diagrams, multi-state systems, system analysis using decision diagrams,
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A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1667-1675 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: pattern matching, virus scanning, index generation function, CAM,
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On the Numbers of Products in Prefix SOPs for Interval Functions Infall SYAFALNI Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/05/01 Vol. E96-D No. 5 pp. 1086-1094 Type of Manuscript: PAPER Category: Computer System Keyword: prefix sum-of-products, number of products by PreSOP, distribution of interval functions, estimating the size of TCAM,
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A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 364-373 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: regular expression, NFA, DFA, MNFAU, FPGA,
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A Quaternary Decision Diagram Machine: Optimization of Its Code Tsutomu SASAO Hiroki NAKAHARA Munehiro MATSUURA Yoshifumi KAWAMURA Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2026-2035 Type of Manuscript: INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Keyword: quarternary decision diagram, branching program machine,
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A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2048-2058 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: embedded system, branching program machine, multi-processing, BDD,
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A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2059-2067 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: two-variable numeric function generators (NFGs), edge-valued multiple-valued decision diagrams (EVMDDs), edge-valued binary decision diagrams (EVBDDs), graph-based representation of numeric functions, programmable memory-based architecture,
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Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2752-2761 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis and Verification Keyword: edge-valued binary decision diagrams (EVBDDs), recursive segmentation, piecewise polynomial approximation, numerical function generators (NFGs), programmable architecture,
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BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades Munehiro MATSUURA Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2762-2769 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis and Verification Keyword: incompletely specified function, characteristic function, binary decision diagram, functional decomposition, LUT cascade,
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Design Methods of Radix Converters Using Arithmetic Decompositions Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/06/01 Vol. E90-D No. 6 pp. 905-914 Type of Manuscript: PAPER Category: Computer Components Keyword: radix converter, LUT cascades, FPGA, functional decomposition,
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A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 932-940 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: three-level networks, AND-EXOR, NP-equivalence, coordinate representation, µ-equivalence, spectral method, logic minimization,
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A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3471-3481 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: LUT cascade, bdd_for_cf, functional decomposition,
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Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3443-3450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, Boolean matching, cell-library binding, technology mapping, canonical form,
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Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3510-3518 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA,
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A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA Hui QIN Tsutomu SASAO Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1139-1147 Type of Manuscript: PAPER Category: Computer Components Keyword: AES encryption, pipelined partial rolling (PPR), FPGA,
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A Design Algorithm for Sequential Circuits Using LUT Rings Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3342-3350 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: reconfigurable architecture, LUT cascade, BDD_for_CF, functional decomposition,
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Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3332-3341 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: AND-EXOR, Reed-Muller expression, FPRM, exact minimization, incompletely specified function,
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Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1492-1500 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: three-level network, logic minimization, adder, programmable logic,
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A Realization of Multiple-Output Functions by a Look-Up Table Ring Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3141-3150 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: LUT cascade, LUT ring, multiple-output function, reconfigurable logic, programmable logic device,
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Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3134-3140 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: Boolean matching, technology mapping, variable permutation, P-equivalence,
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Area-Time Complexities of Multi-Valued Decision Diagrams Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/05/01 Vol. E87-A No. 5 pp. 1020-1028 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: decision diagrams, the number of nodes, area-time complexity, randomly generated function, representation of logic functions,
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Fault Diagnosis for RAMs Using Walsh Spectrum Atsumu ISENO Yukihiro IGUCHI Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 592-600 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Memory Testing Keyword: memory test, diagnosis, BIST, fail-bitmap, Walsh spectrum,
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Compact Representations of Logic Functions Using Heterogeneous MDDs Shinobu NAGAYAMA Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3168-3175 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic and High Level Synthesis Keyword: heterogeneous MDD, ROBDD, FBDD, APL, memory size,
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Bi-Partition of Shared Binary Decision Diagrams Munehiro MATSUURA Tsutomu SASAO Jon T. BUTLER Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2693-2700 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: shared binary decision diagram, SBDD, bi-partition, multiple-output function, decomposition,
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Heuristics to Minimize Multiple-Valued Decision Diagrams Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2498-2504 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: binary decision diagram (BDD), multiple-valued decision diagram (MDD), multiple-output function, multiple-valued logic, FPGA design,
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Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2398-2406 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagram (BDD), characteristic function (CF), multiple-output function, variable ordering, logic simulation, adder, bit-counting function, multiplier,
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Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-D No. 5 pp. 925-932 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Logic Design Keyword: multiple-valued decision diagram (MDD), multiple-valued logic, multiple-output function, time-division multiplexing (TDM),
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FOREWORD Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-D No. 5 pp. 909-909 Type of Manuscript: FOREWORD Category: Keyword:
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Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2545-2553 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: binary decision diagram (BDD), multiple-output functions, clique cover, TDM realization, logic simulation,
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On Properties of Kleene TDDs Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 716-723 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Logic Simulation and Logic Optimization Keyword: binary decision diagram, ternary decision diagram, logic simulation, ternary logic,
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Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/25 Vol. E80-D No. 10 pp. 1001-1008 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Design Keyword: three-level networks, AND-EXOR, logic minimization, complexity of logic networks, NP-equivalence,
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FOREWORD Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/25 Vol. E80-D No. 10 pp. 973-973 Type of Manuscript: FOREWORD Category: Keyword:
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Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm Tsutomu SASAO Debatosh DEBNATH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/25 Vol. E79-A No. 12 pp. 2123-2130 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: AND-EXOR, Reed-Muller expression, complexity of logic networks, logic minimization, binary decision diagrams, easily testable networks,
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Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 pp. 562-570 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic Design Keyword: Reed-Muller expression, AND-EXOR expression, logic minimization, binary decision diagram, symmetric functions,
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