Trong-Yen LEE


Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement
Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 706-716
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock routingdesign for manufacturabilitydouble viaX-architecture
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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
Chia-Chun TSAI Jan-Ou WU Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1  pp. 365-374
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCclock treezero skewgrey relational clusteringDME (deferred-merge embedding)RLC delay model
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Zero-Skew Driven Buffered RLC Clock Tree Construction
Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3  pp. 651-658
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock treeupward propagationbuffer insertionzero skewSoC
 Summary | Full Text:PDF

DESC: A Hardware-Software Codesign Methodology for Distributed Embedded Systems
Trong-Yen LEE Pao-Ann HSIUNG Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/03/01
Vol. E84-D  No. 3  pp. 326-339
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
distributed embedded systemsemulationtwo-level partitioningobject-oriented codesignsoftware scheduling
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Hardware-Software Multi-Level Partitioning for Distributed Embedded Multiprocessor Systems
Trong-Yen LEE Pao-Ann HSIUNG Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 614-626
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
distributed embedded multiprocessor systemmulti-level partitioningcodesignclusteringsharing
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Hardware-Software Timing Coverification of Distributed Embedded Systems
Jih-Ming FU Trong-Yen LEE Pao-Ann HSIUNG Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/09/25
Vol. E83-D  No. 9  pp. 1731-1740
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
hardware-software codesigndistributed embedded systemslinear hybrid automatacoverificationhard deadline
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A New Approach to the Ball Grid Array Package Routing
Shuenn-Shi CHEN Jong-Jang CHEN Trong-Yen LEE Chia-Chun TSAI Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2599-2608
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ball grid array (BGA)pin grid array (PGA)inversion table
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MOBnet: An Extended Petri Net Model for the Concurrent Object-Oriented System-Level Synthesis of Multiprocessor Systems
Pao-Ann HSIUNG Trong-Yen LEE Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/02/25
Vol. E80-D  No. 2  pp. 232-242
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
concurrent object-oriented system-level synthesisconcurrent synthesis modelinghigh-level Petri netsdisign completion checksynthesis rollback
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