IEICE Trans

Toshinori HOSOKAWA

Universal Testing for Linear Feed-Forward/Feedback Shift Registers Hideo FUJIWARA Katsuya FUJIWARA Toshinori HOSOKAWA
Publication: Publication Date: 2020/05/01 Vol. E103-D No. 5 pp. 1023-1030 Type of Manuscript: PAPER Category: Dependable Computing Keyword: linear feed-forward shift registers, linear feedback shift registers, test generation, sequential logic, universal test, built-in self-test, secure scan design,
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A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT Masayoshi YOSHIMURA Yoshiyasu TAKAHASHI Hiroshi YAMAZAKI Toshinori HOSOKAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2824-2833 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: transition faults, correlation, capture power reduction, X-filling, SAT,
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A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation Toshinori HOSOKAWA Atsushi HIRAI Yukari YAMAUCHI Masayuki ARAI
Publication: Publication Date: 2017/09/01 Vol. E100-D No. 9 pp. 2118-2125 Type of Manuscript: PAPER Category: Dependable Computing Keyword: low power, test generation, capture safe test vectors, test vector synthesis, unsafe faults,
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A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution Hiroshi YAMAZAKI Motohiro WAKAZONO Toshinori HOSOKAWA Masayoshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 1994-2002 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: X-bit, don't care identification, X-bit distribution, test compaction,
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A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint Ryoichi INOUE Toshinori HOSOKAWA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 pp. 24-32 Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs) Category: Keyword: state-observable FSMs, logical fault testing, timing fault testing, fault sensitization coverage, n-detection,
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A DFT Selection Method for Reducing Test Application Time of System-on-Chips Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 609-619 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: SoC Testing Keyword: test scheduling, test access mechanism, wrapper, design for test,
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A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint Toshinori HOSOKAWA Hiroshi DATE Masahide MIYAZAKI Michiaki MURAOKA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2674-2683 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, hierarchical test generation,
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Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1474-1482 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test Generation and Modification Keyword: test generation, test plans, compacted test plan tables, test plan compatibility graph, RTL data path,
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Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2722-2730 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: DFT strategies, full scan design methods, partial scan design methods, test point insertions, test application time,
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Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 660-667 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Design for Testability Keyword: design for testability, partial scan design method, n-fold line-up structure, pure load/hold FF,
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