Toshinari TAKAYANAGI


A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array
Kazuhiro SAWADA Toshinari TAKAYANAGI Kazutaka NOGAMI Makoto TAKAHASHI Masanori UCHIDA Yukiko ITOH Tetsuya IIZUKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 929-937
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: ASIC
Keyword: 
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