Toshihiko HIROSE


A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 743-749
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
integrated electronicshigh density SRAMhierarchical bit line organizationT-shaged bit line
 Summary | Full Text:PDF(796.2KB)

A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance
Shigeki OHBAYASHI Tomohisa WADA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1855-1857
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(176.1KB)

A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
Hirotoshi SATO Shuji MURAKAMI Yasumasa NISHIMURA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1858-1860
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(164.1KB)