IEICE Trans

Toshiaki YAMANAKA

A 6.93-µm² Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 590-596 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, full CMOS cell, local interconnect, TiN,
	Summary \| Full Text:PDF

A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits Suguru TACHIBANA Hisayuki HIGUCHI Koichi TAKASUGI Katsuro SASAKI Toshiaki YAMANAKA Yoshinobu NAKAGOME
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 735-738 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
	Summary \| Full Text:PDF

A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 728-734 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
	Summary \| Full Text:PDF

A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers Koichiro ISHIBASHI Kunihiro KOMIYAJI Sadayuki MORITA Toshiro AOTO Shuji IKEDA Kyoichiro ASAYAMA Atsuyosi KOIKE Toshiaki YAMANAKA Naotaka HASHIMOTO Haruhito IIDA Fumio KOJIMA Koichi MOTOHASHI Katsuro SASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/25 Vol. E77-C No. 5 pp. 741-748 Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
	Summary \| Full Text:PDF

A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's Koichiro ISHIBASHI Katsuro SASAKI Toshiaki YAMANAKA Hiroshi TOYOSHIMA Fumio KOJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/25 Vol. E75-C No. 4 pp. 572-575 Type of Manuscript: Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
	Summary \| Full Text:PDF