Toshiaki KAWASAKI

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI
Yasue YAMAMOTO Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Shinichi SUMI Yasuhiro AGATA Hirohito KIKUKAWA Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 1129-1137
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
non-volatile memory, single poly gate, differential cell, CMOS logic process, System-on-Chip (SoC), 
 Summary | Full Text:PDF
A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process
Hiroyuki YAMAUCHI Yasuhiro AGATA Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Kazunari TAKAHASHI Hirohito KIKUKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Vol. E87-C  No. 10  pp. 1664-1672
Type of Manuscript:  Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: CMOS Fuse
Keyword: 
nonvolatile memory, data retention, fuse, CMOS compatible, 
 Summary | Full Text:PDF