Tomonori YONEZAWA

A 90 mW MPEG-4 Video Codec LSI with the Capability for Core Profile
Takashi HASHIMOTO Shunichi KUROMARU Masayoshi TOUJIMA Yasuo KOHASHI Masatoshi MATSUO Toshihiro MORIIWA Masahiro OHASHI Tsuyoshi NAKAMURA Mana HAMADA Yuji SUGISAWA Miki KUROMARU Tomonori YONEZAWA Satoshi KAJITA Takahiro KONDO Hiroki OTSUKI Kohkichi HASHIMOTO Hiromasa NAKAJIMA Taro FUKUNAGA Hiroaki TOIDA Yasuo IIZUKA Hitoshi FUJIMOTO Junji MICHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/07/01
Vol. E86-C  No. 7  pp. 1374-1384
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MPEG-4 visual, core profile, hybrid architecture, clock gating, embedded DRAM, low power, 
 Summary | Full Text:PDF
Low Bit-rate Video Coding Using a DSP for Consumer Applications
Hisashi INOUE Shiro IWASAKI Takashi KATSURA Hitoshi FUJIMOTO Shun-ichi KUROHMARU Masatoshi MATSUO Yasuo KOHASHI Masayoshi TOUJIMA Tomonori YONEZAWA Kiyoshi OKAMOTO Yasuo IIZUKA Hiromasa NAKAJIMA Junji MICHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 708-717
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
digital signal processing, discrete cosine transform, ITU-T H. 261, ITU-T H. 263, symmetric biorthogonal wavelet, subband coding, 
 Summary | Full Text:PDF