Tomohiro KORIKAWA


Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM
Tomohiro KORIKAWA Akio KAWABATA Fujun HE Eiji OKI 
Publication:   
Publication Date: 2021/02/01
Vol. E104-B  No. 2  pp. 149-157
Type of Manuscript:  PAPER
Category: Network System
Keyword: 
cache memorycommunication systemmemory architecturenetwork function virtualization
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