Tomoaki KAWAMURA

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
Yusuke OHTOMO Masafumi NOGAWA Kazuyoshi NISHIMURA Shunji KIMURA Tomoaki YOSHIDA Tomoaki KAWAMURA Minoru TOGASHI Kiyomi KUMOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6  pp. 903-910
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
PON, burst, CDR, IC, CID, 
 Summary | Full Text:PDF(1.5MB)
A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch
Ryusuke KAWANO Naoaki YAMANAKA Eiji OKI Tomoaki KAWAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3  pp. 519-525
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
MCM, ECL interface, high-speed interconnection, noise margin, 
 Summary | Full Text:PDF(836KB)
Advanced ATM Switching System Hardware Technologies Based on MCM-D for ATM Line Interface Circuits
Tomoaki KAWAMURA Naoaki YAMANAKA Katsumi KAIZU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B  No. 2  pp. 482-487
Type of Manuscript:  Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category: Advanced technologies for ATM system
Keyword: 
ATM, MCM, assemble, sub-module, 
 Summary | Full Text:PDF(832.8KB)