Tohru YAMAZAKI


PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
Kazuyuki NAKAMURA Shigeru KUHARA Thoru KIMURA Masahide TAKADA Hisamitsu SUZUKI Hiroshi YOSHIDA Tohru YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 805-811
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
 Summary | Full Text:PDF(685.9KB)

Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs
Kazuyuki NAKAMURA Masahide TAKADA Toshio TAKESHIMA Kouichirou FURUTA Tohru YAMAZAKI Kiyotaka IMAI Susumu OHI Yumi SEKINE Yukio MINATO Hisamitsu KIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 845-852
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
 Summary | Full Text:PDF(808.4KB)