Tohru NAKAMURA


Shallow p-Type Layers in Si by Rapid Vapor-Phase Doping for High-Speed Bipolar and MOS Applications
Yukihiro KIYOTA Tohru NAKAMURA Seiji SUZUKI Taroh INADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 554-559
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
RVDshallow-junction bipolarMOS
 Summary | Full Text:PDF(549.9KB)

Test Structure and Experimental Analysis of Emitter-Base Reverse Voltage Stress Degradation in Self-Aligned Bipolar Transistors
Hiromi SHIMAMOTO Masamichi TANABE Takahiro ONAI Katsuyoshi WASHIO Tohru NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 211-218
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Reliability Analysis
Keyword: 
self-aligned bipolar transistorhot-carrieremitter-base reverse voltage stress
 Summary | Full Text:PDF(636.6KB)

Process and Device Technologies for High Speed Self-Aligned Bipolar Transistors
Tohru NAKAMURA Takeo SHIBA Takahiro ONAI Takashi UCHINO Yukihiro KIYOTA Katsuyoshi WASHIO Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1154-1164
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category: 
Keyword: 
silicon bipolardouble polysiliconhigh speedself-alignment
 Summary | Full Text:PDF(1.1MB)

High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs
Katsuyoshi WASHIO Hiromi SHIMAMOTO Tohru NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 353-359
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Device Technology
Keyword: 
high-speed high-density self-aligned pnpcomplementary bipolar ULSIshigh-speed and low-power performancefully compatibility with npn
 Summary | Full Text:PDF(639.6KB)

Subquarter-Micrometer PMOSFET's with 50-nm Source and Drain Formed by Rapid Vapor-Phase Doping (RVD)
Yukihiro KIYOTA Tohru NAKAMURA Taroh INADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3  pp. 362-366
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
PMOSFETRVDshallow-junction
 Summary | Full Text:PDF(433.3KB)

Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs
Youji IDEI Takeo SHIBA Noriyuki HOMMA Kunihiko YAMAGUCHI Tohru NAKAMURA Takahiro ONAI Youichi TAMAKI Yoshiaki SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1369-1376
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
soft errorSICOSbipolar RAM256 Kbit
 Summary | Full Text:PDF(765.4KB)