Thanyapat SAKUNKONCHAK

Synchronization Verification in System-Level Design with ILP Solvers
Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3387-3396
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
formal verification, SpecC language, event synchronization, Boolean programs, automatic abstraction refinement, assertion-based verification, 
 Summary | Full Text:PDF(380KB)
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams
Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3192-3199
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
SpecC language, event synchronization, difference decision diagrams (DDDs), Boolean programs, abstraction refinement, 
 Summary | Full Text:PDF(838.6KB)
A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate
Thanyapat SAKUNKONCHAK Sawasd TANTARATANA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6  pp. 1479-1487
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
multiplier-free realization, distributed arithmetic, powers-of-two coefficients, ROM's, carry-lookahead adders, 
 Summary | Full Text:PDF(786KB)