IEICE Trans

Tetsuya IIZUKA

A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit Tetsuya IIZUKA Asad A. ABIDI
Publication: Publication Date: 2018/07/01 Vol. E101-C No. 7 pp. 432-443 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: Sampling, sample-and-hold, passive mixer, sampling oscilloscope, N-path mixer, signal flow graph, frequency translation, conversion gain, noise figure, input impedance,
	Summary \| Full Text:PDF

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting Toru NAKURA Tsukasa KAGAYA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 218-223 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: quick start PLL, phase and frequency presetting,
	Summary \| Full Text:PDF

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction Masahiro KANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 292-298 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: signal integrity, resonant power supply noise, triangular active charge injection, DLL, vernier TDC,
	Summary \| Full Text:PDF

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator Md. Maruf HOSSAIN Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2018/02/01 Vol. E101-A No. 2 pp. 410-424 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: sub-ranging ADC, stochastic comparator, yield, probability density function, optimization, calibration,
	Summary \| Full Text:PDF

A PLL Compiler from Specification to GDSII Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2741-2749 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: PLL compiler, PLL synthesis, PWPLL, specification to GDSII,
	Summary \| Full Text:PDF

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring Tomohiko YANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2017/09/01 Vol. E100-C No. 9 pp. 736-745 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-mode circuit, analog front end, integrator, accumulator, time domain, calibration free,
	Summary \| Full Text:PDF

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR Parit KANJANAVIROJKUL Nguyen NGOC MAI-KHANH Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2017/01/01 Vol. E100-A No. 1 pp. 200-209 Type of Manuscript: Special Section PAPER (Special Section on Wideband Systems) Category: Keyword: pulse generation, UWB-IR, CMOS, low duty cycle, energy efficiency, flip-chip devices,
	Summary \| Full Text:PDF

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/08/01 Vol. E97-A No. 8 pp. 1688-1698 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Electron Beam Direct Writing, Character Projection, routing, interconnect, VIA,
	Summary \| Full Text:PDF

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2458-2466 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: electron beam direct writing, character projection, VIA, interconnect, routing,
	Summary \| Full Text:PDF

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme Kazutoshi KODAMA Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1857-1863 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DCO, ADPLL, high frequency resolution enhancement,
	Summary \| Full Text:PDF

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya IIZUKA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 627-634 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring,
	Summary \| Full Text:PDF

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology Tetsuya IIZUKA Satoshi MIURA Ryota YAMAMOTO Yutaka CHIBA Shunichi KUBO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 661-667 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: time-to-digital converter, pulse shrinking, buffer ring,
	Summary \| Full Text:PDF

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1098-1104 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-to-digital converter, TDC, time-difference-amplifier, TDA, time amp,
	Summary \| Full Text:PDF

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter Tetsuya IIZUKA Jaehyun JEONG Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring, NBTI, PBTI,
	Summary \| Full Text:PDF

Cascaded Time Difference Amplifier with Differential Logic Delay Cell Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 654-662 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-difference-amplifier, TDA, time amp,
	Summary \| Full Text:PDF

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3485-3491 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: exact minimum-width transistor placement, Boolean Satisfiability, non-dual CMOS cells,
	Summary \| Full Text:PDF

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/07/01 Vol. E88-A No. 7 pp. 1957-1963 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization,
	Summary \| Full Text:PDF

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3293-3300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: high speed, cell layout synthesis, Boolean Satisfiability, SAT, CMOS logic cell, minimum width,
	Summary \| Full Text:PDF

A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array Kazuhiro SAWADA Toshinari TAKAYANAGI Kazutaka NOGAMI Makoto TAKAHASHI Masanori UCHIDA Yukiko ITOH Tetsuya IIZUKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 929-937 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: ASIC Keyword:
	Summary \| Full Text:PDF