Tetsuya ICHIKAWA


Leakage Analysis of DPA Countermeasures at the Logic Level
Minoru SAEKI Daisuke SUZUKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 169-178
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacksdifferential power analysishardware countermeasureCMOS logic circuitsecond-order DPA
 Summary | Full Text:PDF(752.1KB)

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
Daisuke SUZUKI Minoru SAEKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 160-168
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacksdifferential power analysishardware countermeasuresecond-order DPA random switching logicCMOS logic circuit
 Summary | Full Text:PDF(737.1KB)

The 128-Bit Block Cipher Camellia
Kazumaro AOKI Tetsuya ICHIKAWA Masayuki KANDA Mitsuru MATSUI Shiho MORIAI Junko NAKAJIMA Toshio TOKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1  pp. 11-24
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
block cipherblock cipher designcryptanalysisCamellia
 Summary | Full Text:PDF(706.7KB)