Tetsushi KOIDE


Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image
Masayuki ODAGAWA Takumi OKAMOTO Tetsushi KOIDE Toru TAMAKI Shigeto YOSHIDA Hiroshi MIENO Shinji TANAKA 
Publication:   
Publication Date: 2022/01/01
Vol. E105-A  No. 1  pp. 25-34
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
medical image/video processingcomputer-aided diagnosis system (CAD)convolutional neural network (CNN)support vector machine (SVM)
 Summary | Full Text:PDF(8.9MB)

Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores
Masayuki ODAGAWA Tetsushi KOIDE Toru TAMAKI Shigeto YOSHIDA Hiroshi MIENO Shinji TANAKA 
Publication:   
Publication Date: 2022/01/01
Vol. E105-A  No. 1  pp. 58-62
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
medical image/video processingcomputer-aided diagnosis system (CAD)navigation functionconvolutional neural network (CNN)support vector machine (SVM)customizable embedded digital signal processor (DSP)
 Summary | Full Text:PDF(3.9MB)

A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System
Masayuki ODAGAWA Takumi OKAMOTO Tetsushi KOIDE Toru TAMAKI Bisser RAYTCHEV Kazufumi KANEDA Shigeto YOSHIDA Hiroshi MIENO Shinji TANAKA Takayuki SUGAWARA Hiroshi TOISHI Masayuki TSUJI Nobuo TAMBA 
Publication:   
Publication Date: 2021/04/01
Vol. E104-A  No. 4  pp. 691-701
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer-aided diagnosis systemconvolutional neural networksupport vector machinecustomizable embedded DSPhardware prototyping
 Summary | Full Text:PDF(12.3MB)

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching
Fengwei AN Tetsushi KOIDE Hans Jürgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/09/01
Vol. E95-D  No. 9  pp. 2327-2338
Type of Manuscript:  PAPER
Category: Biocybernetics, Neurocomputing
Keyword: 
multi-prototype learning systemK-means clusteringsoftware-hardware cooperationone nearest neighbor (1-NN)FPGA-implemented coprocessornearest euclidean distance searching
 Summary | Full Text:PDF(1MB)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
Takeshi KUMAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Masaharu TAGAMI Masakatsu ISHIZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/09/01
Vol. E94-D  No. 9  pp. 1742-1754
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
matrix-processing architectureSIMDbit-serial and word-parallelCAMtable-lookup codingcryptographic algorithmAES
 Summary | Full Text:PDF(1.1MB)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1409-1418
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
content addressable memoryCAMmatrix-processing architectureSIMDbit-serial and word-paralleltable-lookup codingDCTHuffman codingJPEG
 Summary | Full Text:PDF(624KB)

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words
Koh JOHGUCHI Hans Jurgen MATTAUSCH Tetsushi KOIDE Tetsuo HIRONAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/11/01
Vol. E90-C  No. 11  pp. 2157-2160
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
multi-port memoryunified cacheSRAMCMOS
 Summary | Full Text:PDF(979KB)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8  pp. 1312-1315
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
DCTfast DCTmatrix-processing engineSIMDbit-serial and word-parallel
 Summary | Full Text:PDF(485KB)

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories
Md. Anwarul ABEDIN Yuki TANAKA Ali AHMADI Shogo SAKAKIBARA Tetsushi KOIDE Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/06/01
Vol. E90-A  No. 6  pp. 1240-1243
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
associative memorypattern matchingfully-parallel searchk-nearest-matches
 Summary | Full Text:PDF(393KB)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 334-345
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
 Summary | Full Text:PDF(2.1MB)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory
Takeshi KUMAKI Yutaka KONO Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 346-354
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
multiportcontent addressable memoryCAMparallel processingSIMDcategorizationbit parallel block paralleltable-lookup-codingHuffman coding
 Summary | Full Text:PDF(1.6MB)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC
Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1612-1619
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
soft errorECCTCAMembeddedDRAM
 Summary | Full Text:PDF(1.2MB)

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation
Takashi MORIMOTO Hidekazu ADACHI Osamu KIRIYAMA Tetsushi KOIDE Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1299-1302
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
image segmentationreal-time image processingparallel processingLSI implementation
 Summary | Full Text:PDF(1.3MB)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features
Kazunari INOUE Hideyuki NODA Kazutami ARIMOTO Hans Jurgen MATTAUSCH Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1332-1342
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
CAMTCAMsignature-matchingnetwork security
 Summary | Full Text:PDF(2.1MB)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOSTernary CAMnetworkrefresh
 Summary | Full Text:PDF(1.3MB)

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation
Takashi MORIMOTO Yohmei HARADA Tetsushi KOIDE Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/02/01
Vol. E87-D  No. 2  pp. 500-503
Type of Manuscript:  LETTER
Category: Image Processing, Image Pattern Recognition
Keyword: 
image segmentationpixel-parallel processingcell-networkLSI implementationdigital CMOS circuit
 Summary | Full Text:PDF(640.8KB)

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanningtiming-driven layoutbuffer insertionwire sizingsimulated annealing
 Summary | Full Text:PDF(389KB)

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints
Jun'ichiro MINAMI Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2569-2576
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
circuit partitioningiterative improvementFM methodtiming constraintpath-cut number
 Summary | Full Text:PDF(475.4KB)

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layoutglobal routingpin assignmenttiming constraintsimulated evolution
 Summary | Full Text:PDF(880.2KB)

Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities
Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1419-1430
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
over-the-cell routingnon-uniform over-the-cell routing capacityplanar routingH-V routingdynamic programming
 Summary | Full Text:PDF(1.1MB)

An Efficient Timing-Driven Global Routing Method for Standard Cell Layout
Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1410-1418
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
standard cell layoutglobal routingtiming constraintsslack distribution0-1 integer linear programming
 Summary | Full Text:PDF(856.1KB)

A Graph Bisection Algorithm Based on Subgraph Migration
Kazunori ISOMOTO Yoshiyasu MIMASA Shin'ichi WAKABAYASHI Tetsushi KOIDE Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2039-2044
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
graph partitioningheuristic algorithmKernighan-Lin algorithmFiduccia-Mattheyses algorithmsubgraph migration
 Summary | Full Text:PDF(576.1KB)

A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2053-2057
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layoutfloorplanningrelative placementtopological constraintstrong respecttentative insertionblock reshaping
 Summary | Full Text:PDF(387.2KB)

An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design
Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1636-1644
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
channel pin assignmentchannel routingchannel densitybuilding-block layout
 Summary | Full Text:PDF(769.3KB)