Tetsuro KAGE


Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills
Atsushi KUROKAWA Toshiki KANAMOTO Tetsuya IBE Akira KASEBE Wei Fong CHANG  Tetsuro KAGE Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3471-3478
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
dummy metaldummy fillinterconnect capacitanceCMP
 Summary | Full Text:PDF(466.8KB)

A Precise Event-Driven MOS Circhit Simulator
Tetsuro KAGE Hisanori FUJISAWA Fumiyo KAWAFUJI Tomoyasu KITAURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 339-346
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
Mos circuit simulationDC-connected componentevent-driventime-step controlmulti-rate behavior
 Summary | Full Text:PDF(677.3KB)

A Parallel BBD Matrix Solution for MIMD Parallel Circuit Simulation
Tetsuro KAGE Junichi NIITSUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/01/25
Vol. E78-A  No. 1  pp. 88-93
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
parallel circuit simulationMIMD parallel computercircuit partitioningbordered-block-diagonal (BBD) matrixLU-decomposition
 Summary | Full Text:PDF(523.2KB)

A Circuit Partitioning Approach for Parallel Circuit Simulation
Tetsuro KAGE Fumiyo KAWAFUJI Junichi NIITSUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 461-466
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
circuit partitioningparallel circuit simulationsubcircuitsinterconnection nodesbordered-block-diagonal (BBD) matrix
 Summary | Full Text:PDF(447.1KB)