Tetsuo HIRONAKA

FOREWORD
Tetsuo HIRONAKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2  pp. 219-219
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA, 
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4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words
Koh JOHGUCHI Hans Jurgen MATTAUSCH Tetsushi KOIDE Tetsuo HIRONAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/11/01
Vol. E90-C  No. 11  pp. 2157-2160
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
multi-port memory, unified cache, SRAM, CMOS, 
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PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model--Design and Implementation of Its Prototype Processor
Kazuya TANIGAWA Tetsuo HIRONAKA Akira KOJIMA Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 830-840
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable architecture, I-PARS execution model, general purpose, PARS architecture, design and implementation, 
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