Teruya TANAKA


Investigations of Optimum Tier Architectures for ASICs
Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11  pp. 2983-2989
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
packing efficiencyinterconnectRent's ruleASICs
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