Teruhiko YAMADA


On Testing of Josephson Logic Circuits Composed of the 4JL Gates
Teruhiko YAMADA Tsuyoshi SASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 749-752
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Diagnosis of VLSI)
Category: 
Keyword: 
Josephson logic circuittestdefect coverage
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A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 817-821
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
fault diagnosisbridging faultCMOScombinational circuit
 Summary | Full Text:PDF

SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 826-831
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault diagnosisgate-level faultcombinational circuitprobing
 Summary | Full Text:PDF