Tatsuya KUNIKIYO


FOREWORD
Tatsuya KUNIKIYO 
Publication:   
Publication Date: 2018/05/01
Vol. E101-C  No. 5  pp. 303-304
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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FOREWORD
Tatsuya KUNIKIYO 
Publication:   
Publication Date: 2017/05/01
Vol. E100-C  No. 5  pp. 416-416
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1349-1358
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STIstressmodelverificationenhancement
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A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO Tetsuya WATANABE Mitsutoshi SHIROTA Masayuki TERAI Tatsuya KUNIKIYO Kiyoshi ISHIKAWA Yoshihide AJIOKA Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3463-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoCinterconnectphysical parameterlow-kcapacitanceresistancelayout parasitic extraction
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Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation
Yasumasa TSUKAMOTO Tatsuya KUNIKIYO Koji NII Hiroshi MAKINO Shuhei IWADE Kiyoshi ISHIKAWA Yasuo INOUE Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 439-446
Type of Manuscript:  Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
embedded SRAMscaling merit3-dimensional interconnect simulation50 and 70 nm technology nodes
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3-D Topography and Impurity Integrated Process Simulator (3-D MIPS) and Its Applications
Masato FUJINAGO Tatsuya KUNIKIYO Tetsuya UCHIDA Eiji TSUKUDA Kenichiro SONODA Katsumi EIKYU Kiyoshi ISHIKAWA Tadashi NISHIMURA Satoru KAWAZU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 848-861
Type of Manuscript:  Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
LSI fabricationprocess simulatortopographyimpurity diffusionsegregationcapacitance
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Nonlocal Impact Ionization Model and Its Application to Substrate Current Simulation of n-MOSFET's
Ken-ichiro SONODA Mitsuru YAMAJI Kenji TANIGUCHI Chihiro HAMAGUCHI Tatsuya KUNIKIYO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3  pp. 274-280
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
nonlocal impact ionizationsubstrate currentMonte Carlo simulationdevice simulationdrift-diffusion model
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Oblique Rotating Ion Implantation Simulation for the Drain Formation of Gate/N- Overlapped LDD MOSFET's Using the Monte Carlo Method
Tatsuya KUNIKIYO Masato FUJINAGA Tetsuya UCHIDA Norihiko KOTANI Yoichi AKASAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/06/25
Vol. E74-C  No. 6  pp. 1662-1671
Type of Manuscript:  Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration)
Category: 
Keyword: 
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