Tatsuo OHTSUKI


Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
Ryuta NARA Kei SATOH Masao YANAGISAWA Tatsuo OHTSUKI Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2481-2489
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
scan-based side-channel attackscan pathtestabilitycryptosystemRSAsecurity
 Summary | Full Text:PDF

A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3238-3247
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
two-level cacheL1/L2cache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3169-3179
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisfloorplandistributed-register architecturegeneralized distributed-register architecturelocal registerlocal controller
 Summary | Full Text:PDF

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3119-3127
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
scan testtest data compressionX-masking
 Summary | Full Text:PDF

A Scan-Based Attack Based on Discriminators for AES Cryptosystems
Ryuta NARA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3229-3237
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
scan-based attackside-channel attackscan chaintestabilitysecuritycryptographyAES
 Summary | Full Text:PDF

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n)
Kazuyuki TANIMURA Ryuta NARA Shunitsu KOHARA Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2304-2317
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
elliptic curve cryptographydual-radixmodular multiplicationMontgomery multiplicationscalabilityunified
 Summary | Full Text:PDF

An L1 Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6  pp. 1442-1453
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
cachecache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3514-3523
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
scan testtest data compressionX-masking
 Summary | Full Text:PDF

A Secure Test Technique for Pipelined Advanced Encryption Standard
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 776-780
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
scan testsecuritytest quality
 Summary | Full Text:PDF

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains
Youhua SHI Nozomu TOGAWA Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 996-1004
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
test data compressiontest channelsscan test
 Summary | Full Text:PDF

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier
Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 243-249
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: System LSIs and Microprocessors
Keyword: 
elliptic curve cryptosystemMontgmery multiplierpublic-key cryptosystemLSI design
 Summary | Full Text:PDF

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition
Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1340-1349
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
processor synthesisinstruction set synthesispacked SIMD-type functional unitpacked SIMD-type instructionhardware/software cosynthesis
 Summary | Full Text:PDF

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis
Hideki KAWAZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 876-884
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
processor synthesispacked SIMD type operationhardware/software partitioninghardware/software cosynthesissub-operation parallelism
 Summary | Full Text:PDF

FPGA-Based Reconfigurable Adaptive FEC
Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3036-3046
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
dynamic reconfigurable systemadaptive FECFPGAReed Solomon codes
 Summary | Full Text:PDF

A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3208-3215
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressionscan chain reconfigurationrun-length codingscan-in power consumption
 Summary | Full Text:PDF

A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3193-3199
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressiontest slicemultiple scan chainATE
 Summary | Full Text:PDF

High-Level Power Optimization Based on Thread Partitioning
Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3075-3082
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
high-level synthesislow powerthread partitioninggated clocks
 Summary | Full Text:PDF

A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths
Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4  pp. 830-836
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardware/software cosynthesisprocessor synthesisheterogeneous datapaths and heterogeneous registers
 Summary | Full Text:PDF

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
 Summary | Full Text:PDF

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3218-3224
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
processor synthesispacked SIMD type instructionhardware/software partitioninghardware/software cosynthesisDSP processor
 Summary | Full Text:PDF

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
Nozomu TOGAWA Kyosuke KASAHARA Yuichiro MIYAOKA Jinku CHOI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3099-3109
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation Accelerator
Keyword: 
retargetable simulatorDSP processorpacked SIMD type instructionhardware/software cosynthesisprocessor synthesis
 Summary | Full Text:PDF

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
Nozomu TOGAWA Takao TOTSUKA Tatsuhiko WAKUI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/05/01
Vol. E86-A  No. 5  pp. 1082-1092
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
content addressable memoryfunctional memorymicro processor corehardware/software cosynthesishardware/software partitioning
 Summary | Full Text:PDF

A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation
Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2655-2666
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
high-level synthesisenergy optimizationarea/time constraints
 Summary | Full Text:PDF

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation
Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2603-2611
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
motion estimationblock-matchingalgorithmarchitectureVHDL
 Summary | Full Text:PDF

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks
Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 827-834
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesispower estimationgated clockswitching activitysequential circuit
 Summary | Full Text:PDF

Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores
Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2639-2647
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
area estimationdelay estimationhardware/software cosynthesisdigital signal processor (DSP)microprocessor
 Summary | Full Text:PDF

A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files
Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2802-2807
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
hardware/software cosynthesishardware/software partitioningdigital signal processor (DSP)register filehardware unit
 Summary | Full Text:PDF

An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares
Nozomu TOGAWA Masayuki IENAGA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5  pp. 1166-1176
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
high-level synthesiscontrol-based hardwarearea/time optimizationschedulingresource allocation
 Summary | Full Text:PDF

CAM Processor Synthesis Based on Behavioral Descriptions
Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2464-2473
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
content addressable memoryfunctional memorybehavioral synthesisbehavioral descriptionhigh-level synthesis
 Summary | Full Text:PDF

A High Performance Embedded Wavelet Video Coder
Tingrong ZHAO Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6  pp. 979-986
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
wavelet transformzerotreeembedded codingmultiresolutionmotion estimationvideo coding
 Summary | Full Text:PDF

A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files
Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3  pp. 442-451
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardware/software cosynthesisprocessor coredigital signal processingtwo types of register files
 Summary | Full Text:PDF

A Hardware/Software Cosynthesis System for Digital Signal Processor Cores
Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2325-2337
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware/software cosynthesishardware/software partitioningprocessor coredigital signal processing
 Summary | Full Text:PDF

A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs
Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3  pp. 473-482
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
technology mappinglogic-blocklookup tablelogic depth
 Summary | Full Text:PDF

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration
Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2563-2575
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
data-flow oriented processhigh-level synthesisdata-flow graph enumerationschedulingresource binding
 Summary | Full Text:PDF

A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6  pp. 1231-1241
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
schedulingresource bindinghigh-level synthesisdata-flow graphgradual time-frame reduction
 Summary | Full Text:PDF

An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications
Nozomu TOGAWA Kayoko HAGI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 873-884
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGAengineering changelayout reconfigurationplacement and routing
 Summary | Full Text:PDF

A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1795-1806
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAtransport processinglayout designplacement and routingperformance optimizationcircuit delay
 Summary | Full Text:PDF

Fast Scheduling and Allocation Algorithms for Entropy CODEC
Katsuharu SUZUKI Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 982-992
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
entropy CODECschedulingallocationcontrol-flow graph
 Summary | Full Text:PDF

A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 494-505
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAmulti-FPGA systemcircuit partitioningpath delaylogic-block replication
 Summary | Full Text:PDF

Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout
Nozumu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2140-2150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAtransport processinglayout designplacement and routing network flow
 Summary | Full Text:PDF

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 321-329
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAtechnology mappinglayoutpath delayperformance optimization
 Summary | Full Text:PDF

A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1765-1776
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAcircuit partitioninglogic-block replicationnetwork flow
 Summary | Full Text:PDF

A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
Shinsuke OHNO Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1755-1764
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Content Addressable Memory (CAM)parallel fault simulationbit reusing strategypipeline propagationhardware engine
 Summary | Full Text:PDF

Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAlook up tabletechnology mappinglayout designplacementglobal routing
 Summary | Full Text:PDF

Experimental Appraisal of Linear and Quadratic Objective Functions Effect on Force Directed Method for Analog Placement
Imbaby I.MAHMOUD Koji ASAKURA Takashi NISHIBU Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4  pp. 719-725
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
Computer Aided Design (CAD)analog circutis and signal processingalgorithms
 Summary | Full Text:PDF

Placement, Routing, and Compaction Algorithms for Analog Circuits
Imbaby I. MAHMOUD Toru AWASHIMA Koji ASAKURA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 894-903
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Algorithms for VLSI Design
Keyword: 
computer aided design (CAD)analog circuits and signal processingalgorithms
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Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method
Toru AWASHIMA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4  pp. 507-512
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computer aided designLSI design technologylayout designcompactionplane-sweep method
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FOREWORD
Shuji TSUKIYAMA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 257-258
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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A VLSI Geometrical Design Rule Verification Accelerated by CAM-Based Hardware Engine
Tetsuro TAKIZAWA Kazuto KUBOTA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A  No. 10  pp. 3072-3077
Type of Manuscript:  Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword: 
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