IEICE Trans

Tatsuo HIGUCHI

Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms Koichi ITO Ayumi MORITA Takafumi AOKI Hiroshi NAKAJIMA Koji KOBAYASHI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/03/01 Vol. E93-A No. 3 pp. 607-616 Type of Manuscript: PAPER Category: Image Keyword: fingerprint recognition, phase-only correlation, feature-based matching, combination of matchers, score-level fusion, biometrics,
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Arithmetic Circuit Verification Based on Symbolic Computer Algebra Yuki WATANABE Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-A No. 10 pp. 3038-3046 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: datapath, arithmetic circuits, formal verification, computer algebra,
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A Palmprint Recognition Algorithm Using Phase-Only Correlation Koichi ITO Takafumi AOKI Hiroshi NAKAJIMA Koji KOBAYASHI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1023-1030 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: biometrics, palmprint recognition, security, image recognition, phase-only correlation,
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Formal Design of Arithmetic Circuits Based on Arithmetic Description Language Naofumi HOMMA Yuki WATANABE Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3500-3509 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: datapaths, formal design, arithmetic circuits, hardware algorithms, hardware description language, module generator,
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Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1645-1654 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: datapaths, arithmetic circuits, addition algorithms, number systems, multiple-valued logic,
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A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System Koichi ITO Masahiko HIRATSUKA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/03/01 Vol. E89-A No. 3 pp. 735-743 Type of Manuscript: Special Section PAPER (Special Section on Multidimensional Signal Processing and Its Application) Category: Signal Processing Algorithm Keyword: reaction-diffusion system, nonlinear dynamics, shortest path search, excitable dynamics,
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A Redox Microarray--An Experimental Model for Molecular Computing Integrated Circuits-- Masahiko HIRATSUKA Shigeru IKEDA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1804-1808 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: molecular electronics, molecular computing, reaction-diffusion dynamics, nonlinear dynamics, analog integrated circuits,
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A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1827-1836 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistors, multiple-valued logic, quantum devices, logic circuits, parallel counters,
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A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1818-1826 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistor (SET), multiple-valued logic (MVL), counter, analytical model, SPICE,
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A Sub-Pixel Correspondence Search Technique for Computer Vision Applications Kenji TAKITA Mohammad Abdul MUQUIT Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/08/01 Vol. E87-A No. 8 pp. 1913-1923 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Image/Visual Signal Processing Keyword: phase-only correlation, phase correlation, image matching, sub-pixel matching, block matching,
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A Fingerprint Matching Algorithm Using Phase-Only Correlation Koichi ITO Hiroshi NAKAJIMA Koji KOBAYASHI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 pp. 682-691 Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing) Category: Digital Signal Processing for Pattern Recognition Keyword: phase-only correlation, phase-only matched filtering, phase correlation, biometrics, fingerprint verification, fingerprint identification,
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Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms Jun SAKIYAMA Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3009-3019 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: computer arithmetic algorithms, parallel counters, multipliers, datapath, VLSI, circuit synthesis,
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High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation Kenji TAKITA Takafumi AOKI Yoshifumi SASAKI Tatsuo HIGUCHI Koji KOBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 pp. 1925-1934 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: image registration, subpixel registration, image matching, phase-only correlation, phase correlation,
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Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 pp. 2001-2010 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: multiple-valued logic, signal processor, FPGAs, FIR filters,
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Fingerprint Restoration Using Digital Reaction-Diffusion System and Its Evaluation Koichi ITO Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 pp. 1916-1924 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: reaction-diffusion system, pattern formation, digital signal processing, digital filters, fingerprint restoration,
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Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/09/01 Vol. E85-A No. 9 pp. 2061-2071 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: multiple-valued logic, arithmetic circuit, evolutionary computation, genetic algorithm (GA),
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Parallel Evolutionary Design of Constant-Coefficient Multipliers Dingjun CHEN Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 508-512 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: evolutionary graph generation, multiplier, PC clusters, canonical signed-digit (CSD) number representation,
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Design of High-Radix VLSI Dividers without Quotient Selection Tables Takafumi AOKI Kimihiko NAKAZAWA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2623-2631 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: computer arithmetic, SRT division, high-radix division, signed-digit number systems, VLSI,
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Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis-- Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2808-2810 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Analog Synthesis Keyword: multiple-valued logic, arithmetic circuits, evolutionary computation, genetic algorithm,
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Digital Reaction-Diffusion System--A Foundation of Bio-Inspired Texture Image Processing-- Koichi ITO Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 1909-1918 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Image/Visual Signal Processing Keyword: reaction-diffusion system, pattern formation, digital signal processing, digital filters,
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Evolutionary Synthesis of Fast Constant-Coefficient Multipliers Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/09/25 Vol. E83-A No. 9 pp. 1767-1777 Type of Manuscript: PAPER Category: Nonlinear Problems Keyword: circuit design, computer arithmetic, arithmetic circuits, evolvable hardware, evolutionary computation,
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Radix-2-4-8 CORDIC for Fast Vector Rotation Takafumi AOKI Ichiro KITAORI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 pp. 1106-1114 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: computer arithmetic, arithmetic circuits, CORDIC, VLSI, digital signal processing,
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Pattern Formation in Reaction-Diffusion Enzyme Transistor Circuits Masahiko HIRATSUKA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/09/25 Vol. E82-A No. 9 pp. 1809-1817 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: molecular computing, molecular devices, reaction-diffusion dynamics, pattern formation, nonlinear signal processing, parallel processing,
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Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture Takafumi AOKI Yoshiki SAWADA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1687-1698 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Configurable Computing and Fault Tolerance Keyword: computer arithmetic, redundant number systems, digital signal processing, FIR filter, FPGAs,
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A Code-Division Multiplexing Technique for Efficient Data Transmission in VLSI Systems Yasushi YUMINAKA Kazuhiko ITOH Yoshisato SASAKI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1669-1677 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Non-Binary Architectures Keyword: VLSI systems, code division multiplexing, m-sequence, new paradigm computing, spread-spectrum image processing,
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FOREWORD Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1597-1598 Type of Manuscript: FOREWORD Category: Keyword:
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Roundoff Error Analysis in the Decoding of Fractal Image Coding Using a Simplified State-Space Model Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-A No. 6 pp. 872-878 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: fractal image coding, iterated function system, roundoff error, state-space approach,
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Evolutionary Design of Arithmetic Circuits Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 798-806 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: circuit design, computer arithmetic, arithmetic circuits, evolvable hardware, evolutionary computation,
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A Perfect-Reconstruction Encryption Scheme by Using Periodically Time-Varying Digital Filters Xuedong YANG Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/01/25 Vol. E81-A No. 1 pp. 192-196 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: perfect-reconstruction encryption, periodically time-varying digital filters, frequency scramble,
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Analysis of Scaling-Factor-Quantization Error in Fractal Image Coding Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/12/25 Vol. E80-A No. 12 pp. 2572-2580 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: fractal image coding, iterated function systems, scaling-factor-quantization error, state-space approach,
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Design and Analysis of Multiwave Interconnection Networks for MCM-Based Parallel Processing Takafumi AOKI Shinichi SHIONOYA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 935-940 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Concept Devices Keyword: parallel processing, interconnection networks, message-passing multiprocessor systems, multichip module (MCM), optical interconnections,
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State-Space Approach to Roundoff Error Analysis of Fractal Image Coding Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/01/25 Vol. E80-A No. 1 pp. 159-165 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: fractal image coding, iterated function systems, roundoff error analysis, state-space approach,
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Evolutionary Digital Filtering Based on the Cloning and Mating Reproduction Masahide ABE Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 370-373 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: adaptive digital filter, system identification, evolution strategies, multi-point search, non-gradient search,
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Design of Multiplierless 2-D State-Space Digital Filters over a Powers-of-Two Coefficient Space Young-Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 374-377 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: multiplierless 2-D state-space digital filters, powers-of-two, genetic algorithm, high-speed operation,
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FOREWORD Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/09/25 Vol. E77-A No. 9 pp. 1415-1416 Type of Manuscript: FOREWORD Category: Keyword:
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Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing Takahiro HANYU Maho KUWAHARA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: multiple-valued logic, dynamic circuits, small latency, cellular array, template matching,
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FOREWORD Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/06/25 Vol. E77-A No. 6 pp. 935-936 Type of Manuscript: FOREWORD Category: Keyword:
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FOREWORD Shuichi UENO Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/03/25 Vol. E77-A No. 3 pp. 445-446 Type of Manuscript: FOREWORD Category: Keyword:
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A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell Satoshi ARAGAKI Takahiro HANYU Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1649-1656 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content-addressable memory, multiple-valued logic, floating-gate MOS, threshold function, logic-value conversion, relational search operation,
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Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing Yasushi YUMINAKA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1133-1143 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: multiple-valued logic, set-valued logic, parallel processing, frequency multiplexing,
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Research Topics and Results on Digital Signal Processing Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/07/25 Vol. E76-A No. 7 pp. 1087-1096 Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: M-D digital filter, multiple-valued logic circuits, signal processor,
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3-D Object Recognition System Based on 2-D Chain Code Matching Takahiro HANYU Sungkun CHOI Michitaka KANEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 pp. 917-923 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Methods and Circuits for Signal Processing Keyword: 3-D object recognition, chain code sequence, normalization, fast fourier transform (FFT), chain code matching, 3-D measurement,
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Unified Scheduling of High Performance Parallel VLSI Processors for Robotics Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 pp. 904-910 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Parallel Processor Scheduling Keyword: minimum-latency architecture, special-purpose VLSI processor, parallel processing, communication time, bus interconnection network,
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FOREWORD Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 pp. 525-526 Type of Manuscript: FOREWORD Category: Keyword:
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Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory Saneaki TAMAKI Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 pp. 548-554 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic Design Keyword: multiple-valued coding, locally computable circuit, unary operation, partition theory, closed chain set,
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Optical Multiplex Computing Based on Set-Valued Logic and Its Application to Parallel Sorting Networks Shuichi MAEDA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 pp. 605-615 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Optical Logic Keyword: optical computing, optoelectronic integrated circuits, set-valued logic, multiple-valued logic, parallel processing,
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Analysis of Multidimensional Linear Periodically Shift-Variant Digital Filters and Its Application to Secure Communication of Images Masayuki KAWAMATA Sho MURAKOSHI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 pp. 326-336 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: digital signal processing, multidimensional digital filters, linear shift-variant system, frequency scramble, secure communication,
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Rule-Programmable Multiple-Valued Matching VLSI Processor for Real-Time Rule-Based Systems Takahiro HANYU Koichi TAKEDA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 472-479 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued encoding, multiple-valued pattern matching, floating-gate MOS devices, programmable delta literal, fully parallel processing,
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Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 455-462 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued MOS current-mode circuit, residue number system, latency, parallel processing, robot vision,
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Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation Takeshi KASUGA Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 428-435 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: robust-fault-tolerant arithmetic circuit, bitonic sorter three-valued distributed coding, safety, scaler multiple-valued current-mode circuit,
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Prospects of Multiple-Valued VLSI Processors Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 383-392 Type of Manuscript: INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: submicron VLSI, interconnection delay, multiple-valued hardware algorithm, parallel VLSI processor, MVL arithmetic and logic circuits,
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FOREWORD Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 345-346 Type of Manuscript: FOREWORD Category: Keyword:
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Design of a Multiple-Valued VLSI Processor for Digital Control Katsuhiko SHIMABUKURO Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/09/25 Vol. E75-D No. 5 pp. 709-717 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: parallel-structure-based VLSI processor, signed-digit arithmetic system, multiple-valued circuit technology, bidirectional current-mode circuits,
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Design of Three-Dimensional Digital Filters for Video Signal Processing via Decomposition of Magnitude Specifications Masayuki KAWAMATA Takehiko KAGOSHIMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/07/25 Vol. E75-A No. 7 pp. 821-829 Type of Manuscript: Special Section PAPER (Special Section on Multidimensional Signal Processing) Category: Design and Implementation of Multidimensional Digital Filters Keyword: design, parallel separable 3-D digital filter, real time video signal processing, decomposition,
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Design and Evaluation of Highly Prallel VLSI Processors for 2-D State-Space Digital Filters Using Hierarchical Behavioral Description Language and Synthesizer Masayuki KAWAMATA Yasushi IWATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/07/25 Vol. E75-A No. 7 pp. 837-845 Type of Manuscript: Special Section PAPER (Special Section on Multidimensional Signal Processing) Category: Design and Implementation of Multidimensional Digital Filters Keyword: two dimensional state-space digital filters, VLSI processors, distributed arithmetic, behavioral description language, logic synthesizer,
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Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/06/25 Vol. E75-A No. 6 pp. 712-719 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91)) Category: Robot Electronics Keyword: minimum-delay-time architecture, VLSI processor for robotics, parallel processing, parallel communication, multiple bus interconnection networks,
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Highly Parallel Collision Detection Processor for Intelligent Robots Michitaka KAMEYAMA Tadao AMADA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/25 Vol. E75-C No. 4 pp. 398-404 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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A Special-Purpose LSI for Inverse Kinematics Computation Michitaka KAMEYAMA Takao MATSUMOTO Hideki EGAMI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/25 Vol. E74-C No. 11 pp. 3829-3837 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
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Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/25 Vol. E74-C No. 11 pp. 3819-3828 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
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A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing Takahiro HANYU Hiroto ISHII Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 918-928 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: ASIC Keyword:
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Controllability, Observability and Model Reduction of Separable Denominator M-D Systems ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/05/25 Vol. E71-E No. 5 pp. 505-513 Type of Manuscript: PAPER Category: Systems and Control Keyword:
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A Unified Approach to the Minimization of Quantization Effects in Separable Denominator Multi-Dimensional Digital Filters ZHAO Qingfu Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/11/25 Vol. E70-E No. 11 pp. 1092-1095 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword:
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Minimization of Sensitivity of 2-D Systems and Its Relation to 2-D Balanced Realizations Tao LIN Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/10/25 Vol. E70-E No. 10 pp. 938-944 Type of Manuscript: PAPER Category: Circuit Theory Keyword:
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Direct Design of Separable Denominator 3-D State-Space Digital Filters ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/04/25 Vol. E70-E No. 4 pp. 411-421 Type of Manuscript: PAPER Category: Circuit Theory Keyword:
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Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/04/25 Vol. E70-E No. 4 pp. 373-375 Type of Manuscript: LETTER Category: Circuit Theory Keyword:
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A New Property of Optimal Realizations of CRSD 2-D Digital Filters and Its Application to the Direct Spatial-Domain Design ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1986/10/25 Vol. E69-E No. 10 pp. 1084-1092 Type of Manuscript: PAPER Category: System Theory Keyword:
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A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier Michitaka KAMEYAMA Oluwole ADEGBENRO Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1985/01/25 Vol. E68-E No. 1 pp. 14-21 Type of Manuscript: PAPER Category: Signal Processing Keyword:
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