Tamotsu NISHIYAMA


High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
Shigeo KUNINOBU Tamotsu NISHIYAMA Takashi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 436-445
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiplierdividerredundant binarymicroprocessor
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