Takuya SAWADA


A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 332-341
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustnesscachevariation tolerance7T/14T SRAM
 Summary | Full Text:PDF

A Step Size Control Method Improving Estimation Speed in Double Talk Term
Takuto YOSHIOKA Kana YAMASAKI Takuya SAWADA Kensaku FUJII Mitsuji MUNEYASU Masakazu MORIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1543-1551
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
echo cancellerdouble talkstep size controlblock length controltarget error level control
 Summary | Full Text:PDF

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation
Takuya SAWADA Taku TOSHIKAWA Kumpei YOSHIKAWA Hidehiro TAKATA Koji NII Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 586-593
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
SRAMImmunityOn chip monitoringBuilt-in self testing
 Summary | Full Text:PDF