Takeshi SAKATA

A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory
Satoru HANZAWA Takeshi SAKATA Tomonori SEKIGUCHI Hideyuki MATSUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/09/01
Vol. E86-C  No. 9  pp. 1886-1893
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
emerging memory, MISS tunnel-diode, hierarchical bit-line structure, twin dummy-cell, 
 Summary | Full Text:PDF
A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuit, timing adjuster, delay line, DDR SDRAM, 
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A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Hiroki FUJISAWA Takeshi SAKATA Tomonori SEKIGUCHI Kazuyoshi TORII Katsutaka KIMURA Kazuhiko KAJIGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
DRAM, ferroelectric memory, high speed, low-power, high-endurance, 
 Summary | Full Text:PDF
The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
Takao WATANABE Masakazu AOKI Katsutaka KIMURA Takeshi SAKATA Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1206-1214
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
DRAM-based neuro-chip, 106-synapse neural network, 1.5-V digital chip, 0.5-µm CMOS design rule, 
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