Takeshi FUJINO


Hierarchical-Masked Image Filtering for Privacy-Protection
Takeshi KUMAKI Takeshi FUJINO 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10  pp. 2327-2338
Type of Manuscript:  Special Section PAPER (Special Section on Security, Privacy and Anonymity in Computation, Communication and Storage Systems)
Category: Privacy, anonymity, and fundamental theory
Keyword: 
privacysurveillance cameramaskhierarchical operationcipher processingprototype system
 Summary | Full Text:PDF(4.4MB)

Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices
Takeshi KUMAKI Kei NAKAO Kohei HOZUMI Takeshi OGURA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3  pp. 593-596
Type of Manuscript:  LETTER
Category: Information Network
Keyword: 
watermarkmax-plus algebramorphological wavelet transformJPEGcompression tolerancemobile device
 Summary | Full Text:PDF(525.8KB)

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication
Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU Takeshi SUGAWARA Mitsuru SHIOZAKI Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A  No. 1  pp. 264-274
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Hardware Based Security
Keyword: 
Physical Unclonable FunctionPUFGlitch PUFPhysical Random Number GeneratorSpartan-3ASpartan-6
 Summary | Full Text:PDF(1.6MB)

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks
Mitsuru SHIOZAKI Kousuke OGAWA Kota FURUHASHI Takahiko MURAYAMA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A  No. 1  pp. 275-283
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Hardware Based Security
Keyword: 
physical unclonable function (PUF)arbiter-PUFXOR arbiter-PUFRG-DTM PUFmachine learning attacksupport vector machine (SVM)logistic regression (LR)
 Summary | Full Text:PDF(1.9MB)

Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System
Ryohei HORI Taisuke UEOKA Taku OTANI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2182-2190
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
via programmable logic devicestructured ASICexclusive-ORmiddle-volume production
 Summary | Full Text:PDF(3.1MB)

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation
Ryohei HORI Tatsuya KITAMORI Taisuke UEOKA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9  pp. 1518-1528
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
via programmable logic devicestructured ASICmiddle volume production
 Summary | Full Text:PDF(2.2MB)

High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications
Mitsuru SHIOZAKI Kota FURUHASHI Takahiko MURAYAMA Akitaka FUKUSHIMA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 468-477
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Physical Unclonable Function (PUF)Arbiter-PUFHigh UniquenessResponses Generation according to the Delay-Time Measurement (RG-DTM) scheme
 Summary | Full Text:PDF(2.2MB)

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing
Akihiro NAKAMURA Masahide KAWARASAKI Kouta ISHIBASHI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 509-516
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
via-programmable logicelectron-beam direct writinglow volume productionexclusive ORstructured ASIClook-up table
 Summary | Full Text:PDF(1.2MB)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs
Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2991-3000
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
embedded memoryDRAMlow powersystem on chip
 Summary | Full Text:PDF(2.9MB)

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1697-1708
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAMsystem on chip3-D graphics concurrent operation
 Summary | Full Text:PDF(2.2MB)