Takeo YASUDA


An On-Chip Power-on Reset Circuit for Low Voltage Technology
Takeo YASUDA Masaaki YAMAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2  pp. 366-372
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
power-on resetlow voltagestate initialization
 Summary | Full Text:PDF

A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2793-2801
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
Keyword: 
PLLphase adjustvariable delaylock-up
 Summary | Full Text:PDF

High-Speed Wide-Locking Range VCO with Frequency Calibration
Takeo YASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2616-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword: 
VCOPLLhigh speedwide locking rangecalibration
 Summary | Full Text:PDF

Differential Analog Data Path DC Offset Calibration Methods
Takeo YASUDA Hajime ANDOH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 301-306
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
DC offset cancelanalog differential pathHDD channeloffset calibration
 Summary | Full Text:PDF