Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design Norio OHKUBOTakeo YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-CNo. 4pp. 618-623 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: delay calculation, effective capacitance, logic circuit optimization, delay optimization, LSI design,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/25 Vol. E83-CNo. 11pp. 1747-1754 Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: CMOS, threshold voltage, leakage current, low power,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/07/25 Vol. E75-CNo. 7pp. 839-843 Type of Manuscript: Special Section PAPER (Special Issue on Ultra Clean Technology) Category: Keyword: ion energy, ion flux, contamination, ion energy-flux parameter map,
