Takehisa YAMAGUCHI


Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 812-817
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
SOISIMOXSRAMlow-voltage operationback-gate bias effect
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A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation
Masahiro SHIMIZU Takehisa YAMAGUCHI Masahide INUISHI Katsuhiro TSUKAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4  pp. 532-540
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
MOS transistorshallow junctionsalicidetitanium
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