IEICE SEARCH SYSTEM

Takashi SATO

Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption Song BIAN Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2019/02/01 Vol. E102-A No. 2 pp. 430-439 Type of Manuscript: PAPER Category: Cryptography and Information Security Keyword: homomorphic encryption, secure naive bayesian filter, secure email classification, asic multiplier,
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MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator Masayuki HIROMOTO Motoki YOSHINAGA Takashi SATO
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1035-1044 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: physically unclonable function (PUF), chip identification, machine learning attacks, ring oscillator,
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Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update Satoshi YAMAMORI Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1092-1100 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: memoristor, neural network, mini-batch training, stochastic gradient descent,
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Area Efficient Annealing Processor for Ising Model without Random Number Generator Hidenori GYOTEN Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2018/02/01 Vol. E101-D No. 2 pp. 314-323 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Device and Architecture Keyword: combinatorial optimization problem, max-cut problem, Ising model, annealing, FPGA,
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Identification and Application of Invariant Critical Paths under NBTI Degradation Song BIAN Shumpei MORITA Michihiro SHINTANI Hiromitsu AWANO Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2797-2806 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: NBTI, aging effect, invariant critical path, processor,
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Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation Hiromitsu AWANO Takashi SATO
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2807-2815 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: failure probability calculation, NBTI, Monte Carlo, subset simulation, augmented reliability,
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Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation Shumpei MORITA Song BIAN Michihiro SHINTANI Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1464-1472 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: NBTI mitigation, reliability, transistor aging, performance degradation, internal node control,
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Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling Hiromitsu AWANO Masayuki HIROMOTO Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1390-1399 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: SRAM cell yield, failure probability calculation, NBTI, importance sampling, particle filter, Monte Carlo method,
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Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability Song BIAN Michihiro SHINTANI Masayuki HIROMOTO Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1400-1409 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: NBTI, reliability, static timing analysis, timing characterization, aging-aware timing library,
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An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 741-750 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: coarse-grained reconfigurable architecture, reliability, triple modular redundancy, immediate termination, error-critical period,
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Automation of Model Parameter Estimation for Random Telegraph Noise Hirofumi SHIMIZU Hiromitsu AWANO Masayuki HIROMOTO Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2383-2392 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: random telegraph noise (RTN), Gaussian mixture model (GMM), expectation-maximization (EM) algorithm, information criteria, model estimation,
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IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination Michihiro SHINTANI Takashi SATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/08/01 Vol. E97-D No. 8 pp. 2095-2104 Type of Manuscript: PAPER Category: Dependable Computing Keyword: IDDQ testing, k-means clustering, statistical leakage current analysis, Bayes' theorem, simulated annealing,
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Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 280-288 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for manufacturing, Monte Carlo method, importance sampling, SRAM, process variation, yield, norm minimization, Gaussian mixture models, clustering, hypersphere sampling,
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State-Dependence of On-Chip Power Distribution Network Capacitance Koh YAMANAGA Shiho HAGIWARA Ryo TAKAHASHI Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/01/01 Vol. E97-C No. 1 pp. 77-84 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: CMOS logic circuit, state-dependent capacitance model, capacitance measurement, PDN-capacitance, parasitic capacitance,
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A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 454-462 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: soft error, single event upset, triple modular redundancy, reliability, simulated annealing,
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Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 473-481 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: statistical static timing analysis, delay distribution, slew rate, field-programmable gate array, Mersenne Twister,
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Device-Parameter Estimation through IDDQ Signatures Michihiro SHINTANI Takashi SATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/02/01 Vol. E96-D No. 2 pp. 303-313 Type of Manuscript: PAPER Category: Dependable Computing Keyword: IDDQ testing, statistical leakage current analysis, Bayes' theorem,
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A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2242-2250 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: subthreshold operation, process variation, minimum operation voltage estimation, energy minimization, yield maximization,
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Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method Hiromitsu AWANO Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2272-2283 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: random telegraph noise, Bayesian estimation, Markov chain Monte Carlo, device characterization, source separation, statistical machine learning,
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Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis Takashi ENAMI Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2261-2271 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power distribution network, decoupling capacitance, timing analysis, statistical static timing analysis, decap insertion, wire sizing,
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Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence Shiho HAGIWARA Koh YAMANAGA Ryo TAKAHASHI Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2409-2416 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: capacitance, power distribution network, state-dependency, integrated circuit modeling, electromagnetic interference,
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Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2524-2532 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: soft error, TMR, reliability, methodology,
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A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation Takumi UEZONO Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 324-331 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: voltage measurement, spatial voltage drop fluctuation, process variation, power/signal integrity,
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A Universal Equivalent Circuit Model for Ceramic Capacitors Koh YAMANAGA Shuhei AMAKAWA Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 347-354 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: ceramic capacitor, moment method, equivalent circuit, inductance,
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Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
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Fingerprinting Codes for Internet-Based Live Pay-TV System Using Balanced Incomplete Block Designs Shuhui HOU Tetsutaro UEHARA Takashi SATOH Yoshitaka MORIMURA Michihiko MINOH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 876-887 Type of Manuscript: Special Section PAPER (Special Section on Information and Communication System Security) Category: Contents Protection Keyword: fingerprinting code, anti-collusion code, BIBD, unital, affine plane,
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Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits Shiho HAGIWARA Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1031-1038 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: device parameter variation, MTCMOS, timing analysis, Monte-Carlo simulation,
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2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept Koh YAMANAGA Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 976-982 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: ceramic capacitor, inductance, impedance, power distribution network,
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
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One-Shot Voltage-Measurement Circuit Utilizing Process Variation Takumi UEZONO Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1024-1030 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: voltage measurement, process variation, power/signal integrity,
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Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress Kenta YAMADA Takashi SATO Shuhei AMAKAWA Noriaki NAKAYAMA Kazuya MASU Shigetaka KUMASHIRO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/07/01 Vol. E91-C No. 7 pp. 1142-1150 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: STI, stress, modeling, SPICE, layout-aware,
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Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network Shiho HAGIWARA Takumi UEZONO Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 951-956 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: voltage drop analysis, power distribution network, correlation coefficient, multiple regression,
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An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis Masanori IMAI Takashi SATO Noriaki NAKAYAMA Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 957-964 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, STA, Monte Carlo STA, timing analysis, ranking,
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Timing Analysis Considering Temporal Supply Voltage Fluctuation Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 655-660 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Verification and Timing Analysis Keyword: timing analysis, dynamic power supply noise,
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Proposal of Metrics for SSTA Accuracy Evaluation Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 808-814 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: statistical static timing analysis, statistical max operation, DFM, SoC,
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On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature Takashi SATO Junji ICHIMIYA Nobuto ONO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3491-3499 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: thermal gradient simulation, leakage power, temperature-dependent leakage power, power calculation, leakage model,
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A Method to Derive SSO Design Rule Considering Jitter Constraint Koutaro HACHIYA Hiroyuki KOBAYASHI Takaaki OKUMURA Takashi SATO Hiroki OKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 865-872 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: simultaneous switching output, simultaneous switching noise, jitter, ASIC,
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On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design Takashi SATO Junji ICHIMIYA Nobuto ONO Koutaro HACHIYA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3382-3389 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: thermal simulation, thermal gradient, temperature flattening, clock skew, reliability, timing,
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Successive Pad Assignment for Minimizing Supply Voltage Drop Takashi SATO Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3429-3436 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power/Ground Network Keyword: successive pad assignment (SPA), incremental matrix inversion (IMI), voltage drop, power distribution network,
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Development of Autocloned Photonic Crystal Devices Takayuki KAWASHIMA Yoshihiro SASAKI Kenta MIURA Naoki HASHIMOTO Akiyoshi BABA Hiroyuki OHKUBO Yasuo OHTERA Takashi SATO Wataru ISHIKAWA Tsutomu AOYAMA Shojiro KAWAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/03/01 Vol. E87-C No. 3 pp. 283-290 Type of Manuscript: INVITED PAPER (Special Section on Photonic Crystals and Their Device Applications) Category: Keyword: photonic crystal, autocloning, polarizer, waveguide,
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Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances Atsushi KUROKAWA Takashi SATO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2933-2941 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: on-chip inductance, parasitic extraction, VLSI interconnects, inductance extraction,
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Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects Atsushi KUROKAWA Kotaro HACHIYA Takashi SATO Kazuya TOKUMASU Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 841-845 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: inductance, parasitic extraction, VLSI interconnect, geometric mean distance, skin effect,
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Frontiers Related with Automatic Shaping of Photonic Crystals Osamu HANAIZUMI Kenta MIURA Makito SAITO Takashi SATO Shojiro KAWAKAMI Eiichi KURAMOCHI Satoshi OKU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/06/25 Vol. E83-C No. 6 pp. 912-919 Type of Manuscript: INVITED PAPER (Special Issue on Advanced Optical Devices for Next Generation High-Speed Communication Systems and Photonic Networks) Category: Switches and Novel Devices Keyword: autocloning, TiO₂/SiO₂ photonic crystal, phase plate, polarization selective grating, CdS, photoluminescence,
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Highly Nonlinear Vector Boolean Functions Takashi SATOH Kaoru KUROSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 807-814 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: Boolean function, bent function, balancedness, nonlinearity,
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Towards Secure and Fast Hash Functions Takashi SATOH Mio HAGA Kaoru KUROSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/01/25 Vol. E82-A No. 1 pp. 55-62 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: cryptanalysis, hash function, block cipher, meet-in-the-middle attack, birthday attack,
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Generalization of Higher Order SAC to Vector Output Boolean Functions Kaoru KUROSAWA Takashi SATOH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/01/25 Vol. E81-A No. 1 pp. 41-47 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: Strict Avalanche Criterion (SAC), vector output function,
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Information Theoretic Approach to Privacy for Multi-Party Protocols Takashi SATOH Kaoru KUROSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/01/25 Vol. E80-A No. 1 pp. 79-84 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: multi-terminal information theory, privacy, multiparty protocol,
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Attack on Yagisawa Cryptosystem Kaoru KUROSAWA Takashi SATOH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/01/25 Vol. E80-A No. 1 pp. 107-108 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: Yagisawa cryptosystem, Kannan's algorithm,
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Multimedia Database Systems for the Contents Mediator Masao SAKAUCHI Takashi SATOU Yoshitomo YAGINUMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/06/25 Vol. E79-D No. 6 pp. 641-646 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia Computing and Communications) Category: Keyword: multimedia database, mediator, digital broadcasting, stream-type multimedia DB, realworld multimedia DB, live hypermedia, intelligent video authoring,
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Communication Complexity of Perfect ZKIP for a Promise Problem Kaoru KUROSAWA Takashi SATOH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/01/25 Vol. E76-A No. 1 pp. 46-49 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: communication complexity, perfect ZKIP promise problem, quadratic residuosity,
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