Takashi OHSAWA


Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching Probability
Haoyan LIU Takashi OHSAWA 
Publication:   
Publication Date: 2021/03/01
Vol. E104-C  No. 3  pp. 121-127
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
magnetic tunnel junctions (MTJ)spin transfer torque magnetic random-access memory (STT-MRAM)modelingVerilog-A
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Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
Yue GUAN Takashi OHSAWA 
Publication:   
Publication Date: 2020/11/01
Vol. E103-C  No. 11  pp. 685-692
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
neuromorphic ReRAMbinary neural networkfabrication fluctuation
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Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme
Ziyue ZHANG Takashi OHSAWA 
Publication:   
Publication Date: 2020/08/01
Vol. E103-C  No. 8  pp. 372-380
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
dummy cell average read schemeCBLSASTT-MRAMarray designhigh access speed
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A New Read Scheme for High-Density Emerging Memories
Takashi OHSAWA 
Publication:   
Publication Date: 2018/06/01
Vol. E101-C  No. 6  pp. 423-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ReRAMSTT-MRAMPCRAMmemristorreference celldummy cellredundancybit yieldweighted average
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Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating
Shuta TOGASHI Takashi OHSAWA Tetsuo ENDOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5  pp. 854-859
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
MTJnonvolatilefine-grained power gatingcounter unitlow power
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Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
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A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
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