IEICE Trans

Takashi NANYA

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times Hiroshi SAITO Naohiro HAMADA Nattha JINDAPETCH Tomohiro YONEDA Chris MYERS Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2790-2799 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: asynchronous circuits, scheduling, start times, and control steps,
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Design Method of High Performance and Low Power Functional Units Considering Delay Variations Kouichi WATANABE Masashi IMAI Masaaki KONDO Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3519-3528 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: delay variation, dual-rail asynchronous circuit, functional unit, unflip-bit control,
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Evaluation of Checkpointing Mechanism on SCore Cluster System Masaaki KONDO Takuro HAYASHIDA Masashi IMAI Hiroshi NAKAMURA Takashi NANYA Atsushi HORI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2553-2562 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Dependable Software Keyword: checkpointing, rollback-recovery, cluster system, high availability,
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Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3028-3037 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: asynchronous controllers, logic synthesis, Control Data Flow Graphs (CDFGs), Signal Transition Graphs (STGs),
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Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits Nattha SRETASEREEKUL Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 900-907 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: isochronic forks, asynchronous circuits, quasi-delay-insensitive circuits,
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Design of Asynchronous Controllers with Delay Insensitive Interface Hiroshi SAITO Alex KONDRATYEV Jordi CORTADELLA Luciano LAVAGNO Alex YAKOVLEV Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2577-2585 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Design Methodology Keyword: DI interface, signal transition graph, hazards, behavioral and gate-level transformations,
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A Cascade ALU Architecture for Asynchronous Super-Scalar Processors Motokazu OZAWA Masashi IMAI Yoichiro UENO Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 229-237 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: asynchronous, superscalar processor, cascade ALU, fine grain pipeline,
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A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase Rafael K. MORIZAWA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2446-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Methodology Keyword: asynchronous circuit, asynchronous specification, logic synthesis, CAD tool,
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On Concurrent Error Detection of Asynchronous Circuits Using Mixed-Signal Approach B. Ravi KISHORE Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 pp. 351-362 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Completion-Detection & Checking Keyword: concurrent error detection, QDI circuits, current sensing, built-in current sensors,
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Synthesis of Asynchronous Circuits from Signal Transition Graph Specifications Sung-Bum PARK Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 pp. 326-335 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Synthesis Keyword: asynchronous synthesis, logic synthesis, signal transition graphs, Petri nets, speed-independent circuits,
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FOREWORD Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 pp. 285-286 Type of Manuscript: FOREWORD Category: Keyword:
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FOREWORD Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/25 Vol. E80-D No. 1 pp. 1-2 Type of Manuscript: FOREWORD Category: Keyword:
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A Design Method of SFS and SCD Combinational Circuits Shin'ichi HATAKENAKA Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/25 Vol. E75-D No. 6 pp. 819-823 Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems) Category: Keyword: self-checking circuits, strongly fault-secure, strongly code-disjoint, combinational circuits, concurrent error detection,
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